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8: DMA Controller
92 GP4020 GPS Baseband Processor Design Manual
1.1.4) Clear to “0” the Receive Interrupt Enable bit (bit 4) to disable interrupts generated when the UART
receive register is full.
1.1.5) Clear to “0” the Modem Interrupt Enable bit (bit 7) and the Error Interrupt Enable bit (bit 6) to disable
interrupts from a remote modem or a UART error.
1.2) Set-up the appropriate UART baud rates, data lengths, stop bits, parity, etc using the Serial Mode Register
(MR) and Baud Rate Register (BRR); ref. Table 17.1 on page 170 thru to Table 17.11 on page 174 for
settings.
2) Set-up the source of DMAC Triggering (i.e. the prompt that initiates the DMA transfers following the DMAC
program cycle). The GP4020 DMAC can take triggers from both software and Hardware sources. For DMA
Fly-by transfers using UART 1 as a peripheral, DMAC Channel 1 must be used. Similarly if using UART 2 as a
peripheral, DMAC Channel 2 must be used.
2.1) If software triggering is required (and not hardware triggering), this can be programmed explicitly into the
DMAC (refer to Section 8.3 "DMAC Triggering" on page 99).
2.2) DMAC Channel 1 has the flexibility of being able to undertake Fly-by transfers using Hardware triggering
from a number of different sources. The trigger source required can be selected by setting up the DMAC
Trigger Source bits within the System Configuration Register (SCR) (Address 0xE000 2004) in the System
Services Module (SSM). In most cases, for fly-by transfers, it is most appropriate to use UART 1 as the
DMAC Trigger Source. However, the options shown in Table 8.1 Hardware Trigger Source selection for
DMAC Channel 1" below add flexibility to this.
SCR[5:2] DMAC Channel 1 Trigger Source
0011 UART 2 Transmit / Receive.
Function is determined by UART 2 interrupt type.
0101
SYSTIC 1A interrupt
(see note 1)
0111 UART 1 Receive
1001 RF_PLL_LOCK interrupt
1011 EXTINT2 input interrupt
1101
SYSTIC 2A interrupt
(see note 1)
1111 UART 1 Transmit
Table 8.1 Hardware Trigger Source selection for DMAC Channel 1
Note 1: Refer to Section 7 of the Firefly MF1 Core Design Manual (DM5003) for details of how to employ the
Firefly TIC (SYSTIC) timer function. This can essentially provide regular time intervals, from which the
DMAC can then trigger.
2.3) DMAC Channel 2 can only receive DMAC hardware triggers from UART 2, and no other source.
Consequently, the only trigger option avails listed in Table 8.1 above do not exist for UART 2 DMAC Fly-
by transfers.
3) Put DMAC into “Program Mode” to allow DMA commands to be programmed into DMAC before execution.
This is done by clearing to ”0” the Channel Status bit (bit 0) of the Channel and Control Status Register (CSR)
for the relevant DMAC Channel (UART1 uses Channel 1, UART 2 uses Channel 2).
This allows the DMAC to be programmed with commands, and DMAC operations are suspended until bit 0 is
set to a “1”.
Program the DMAC Channel for a Write data transfer from memory to UART 1 (or 2) for TX:
3.1) For the DMAC Channel 1 (or 2) Control and Status Register (CSR):