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5: The BµILD BUS
32 GP4020 GPS Baseband Processor Design Manual
Example slave devices are:
• UART
• Memory / Peripheral Controller
• General Purpose Input Output
5.3 Bus Signals
The BµILD bus, internal to the GP4020 has full 32-bit un-multiplexed address and data busses, b_addr<31:0> and
b_data<31:0>. The direction of the current transaction is denoted by a write not read signal, b_write. The BµILD
bus also supports multiple transaction sizes of byte, half-word (16-bits) and word (32-bits), as denoted by
b_size<1:0>. Along with these main control signals are a number of additional control signals such as
b_mode<2:0> that specifies the current bus-operating mode. In addition, two control signals are driven by the
current bus slave, b_wait and b_error. b_wait is used to denote that wait states must be inserted in to the current
bus access while b_error is used to denote that the current bus transaction is illegal e.g. a write to a read-only
register.