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12: Peripheral Control Logic
GP4020 GPS Baseband Processor Design Manual 123
Note: the WATCH_EN bit in only effects Watchdog behaviour due to Firefly reset. (If WATCH_EN is set to '1',
the Watchdog starts immediately. If WATCH_EN is '0', Watchdog will only start after the RESTART KEY value
is written to it).
h) Firefly and Correlator block reset, due to NRESET. This feature cannot be disabled.
12.6 Chip-wide Power Control modes
The GP4020 incorporates a number of disable and power-saving modes.
12.6.1 Full Power-Down
A Full Power-down of the GP4020 (i.e. Clocks removed from the whole chip, except for the Real Time Clock) can
be made to occur, if a '1' is written to the POWG_EN bit (POW_CNTL[15]), and the POWER_GOOD input (pin 64
(100-pin package)) is set Low. Under these conditions, the following pins on the GP4020 get set as shown (pin
numbers refer to 100-pin package):
• Set as High Impedance (i.e. Tristate):
NSCS[0] (pin 11), NSCS[1] (pin 12), NSCS[2A] (pin 13), NSOE (pin 25), NSWE[1] (pin 26), NSWE[0] (pin
27), NSUB (pin 52),
• Set to Logic Low:
SAMPCLK (pin 63), U2TXD (pin 76), U1TXD (pin 78),
In this mode, DISCIO can be configured to output a '1' to power down an RF Front-end IC (achieved if
DISCIO_CFG[2:0] in IO_REV register is set to '100'. It is strongly recommended that if a RF Front-end power-down
function is required, a 1kohm pull-down resistor should be connected to DISCIO. The reset condition of the GP4020
is to make DISCIO pin an input, which will mean that voltage on PDn input on RF Front-end could be >+0.8V if no
resistor was present, and the RF IC could be disabled.
Note: the DISCIO configuration (i.e. output RF_PDOWN / input), is only reset by an NPOR_RESET event.
In the GP2010 and GP2015 GPS RF Front-end ICs, the Power-on Reset circuitry is NOT disabled by an RF Power
Down, and so POWER_GOOD will still indicate a valid state, whilst main-power is still present. The
POWER_GOOD signal originates from the RF Front-end, and the incidence of a POWER_GOOD failure will
normally suggest that Main Power has been lost from the whole GPS receiver. On restoration of POWER_GOOD,
there will be a delay of approx. 5ms while the RF Front-end PLL locks up to the 10.00MHz TCXO.
If POWG_EN is set to '0', the POWER_GOOD input will NOT power-down the GP4020.