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15: 1PPS Timemark Generator
GP4020 GPS Baseband Processor Design Manual 155
15.4 Fine-resolution Timemark setting, using TIC period slewing
15.4.1 Functional description
The GP4020 includes some logic within the 1PPS Timemark Generator which allows the TIC period to be specified
to a resolution of 1 M_CLK cycle (25ns), without significantly affecting the existing logic in the correlator core.
The default period of TIC is set to be 99999.9µs. Hence it will normally be necessary to add an extra 100ns to the
effective period of TIC. This ensures that once every 10 TIC periods, there will be one Timemark output signal that
occurs at exactly a one-second period.
A Modulo 7 adder, clocked by TIC from the 12-channel correlator in conjunction with a Timemark delay latch which
is clocked by M_CLK (40MHz), can produce "phase-delays" in steps of 25ns into the RAW TIMEMARK signal. The
TIC_CORR register can be used to specify the number of M_CLK cycle events (25ns period) to add to each TIC
event (up to 175ns). In a typical case, where RAW_TIMEMARK is outputted once every 10 TICs, this gives a
maximum adjustment range of delay of 0ns to 1750ns.
At each TIC event, the value in TIC_CORR is added to the existing "Phase_offset". If the result of the addition is
greater than or equal to 7, an overflow flag (RELOAD_TIC) is generated. When RELOAD_TIC is set, the load
signal to the TIC Generator counter can stay active for an extra TIC cycle. This has a similar result to incrementing
the TIC Generator period by 175ns for one TIC period (same effect as incrementing the TIC Generator register
"PROG_TIC_LOW" by 1, for one TIC period). The GPS software will normally need to know when the period of TIC
is modified by this overflow function, and there are 2 facilities provided for identifying when TIC slewing has
occurred / will occur:
1) The interrupt signal TIC_INT is set. This is configured by the PCL block to interrupt the Firefly core, which
could then run a simple Interrupt Service Routine, to inform the GPS software that TIC will be 100000.075µs
period for one TIC only. (TIC_INT is cleared by a write to CLR_INT (bit 11 in the PER_STAT register).
2) The ADJ_TIC bit (Bit 1 in the TIC_RET register) is set.
At any given time, the current phase_offset can be read from PHASE_OFF[2:0] in TIC_RET register (bits 0 to 2).
If a RAW_TIMEMARK output is produced from the Raw Timemark Generator on the 12-channel correlator block at
a given TIC event, the value of "Phase_offset" is latched, and delivered to a 7-stage delay block (Timemark delay),
clocked by M_CLK (40MHz). The RAW_TIMEMARK signal is then delayed by between zero and 6 x 25ns using the
delay block. Note: the TIMEMARK output will always have an additional half M_CLK cycle delay to allow for re-
timing into the Timemark Delay block.
The Timemark delay block is always enabled. However, if a TIMEMARK delay is not required, TIC_CORR can be
set to '000', which will give zero M_CLK cycle delays to the RAW_TIMEMARK signal, and hence TIMEMARK =
RAW_TIMEMARK.
15.4.2 TIC period slewing Configurations for approximate alignment to 1PPS
This section shows how to configure the 1PPS Timemark generator to produce a Timemark, which is approximately
one pulse per second in period, using TIC period slewing. The considerations of aligning time-mark to UTC are
NOT covered here, so the Timemark is only approximately 1PPS. The accuracy of the GPS receiver TCXO (which
drives the RF Front-end), limits the accuracy of the 1PPS Timemark output. Timemark setting examples, later in
this section, illustrate the different scenarios for UTC alignment of Timemark to UTC.
The TIC period slewing correction logic can be configured to work in a number of ways. The ADJ_TIC bit in the
TIC_RET register behaves differently for reads and writes, so the following sections use ADJ_TIC_WR (for write to
ADJ_TIC) and ADJ_TIC_RD (for read from ADJ_TIC), although they both refer to the same bit in TIC_RET register.
If TIC_INT_EN[1:0] = '00' (in PER_STAT register), the TIC period will not be corrected, since the RELOAD_TIC
and TIC_INT signals from the Overflow control logic will be both disabled. However, since the Timemark delay
block is always enabled, if TIC_CORR is not set to '000', the RAW_TIMEMARK will be set by (TIC_CORR DIV 7).