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7: 12-Channel Correlator
76 GP4020 GPS Baseband Processor Design Manual
If a channel is inactive, a non-zero slew value should be written into CHx_CODE_SLEW before the channel is
released. This write will be acted on immediately the reset is released.
If a TIC occurs during or soon after a slew, the channel will not be locked to the satellite, so the Measurement Data
for that channel will not be of use.
The ability to read the Slew counter is included only for testing hardware or software and has no other use. It will
only give a non-zero result if the read occurs during the actual slew operation. An example of a slewing event is
shown in Figure 7.5 below.
1023 CHIPS 1025.5 CHIPS
TIME
DUMPDUMPDUMP
t1
1021 1022 1023 0 1 2 30000
CODE-SLEW EVENT
5 HALF-CHIP SLEWS
= 2.5CHIPS
C/A CODE CHIP NO.
At time t1, Load '5' into
CHx_CODE_SLEW register
(= 2.5 chips delay)
DUMP
Figure 7.5 Slew timing in UPDATE Mode
Bit
No.
Mnemonic Description Reset
Value
R/W
15:11
Not used
-W
10:0 CHx_CODE_SLEW _COUNTER [10:0] Bits 10:0 of the 11-bit Code Slew
Count, in steps of half a chip.
0x000 W
Table 7.22 CORR CHx_CODE_SLEW_COUNTER Register
Bit
No.
Mnemonic Description Reset
Value
R/W
15:11
Not used
'0' when read. - R
10:0 CHx_CODE_SLEW[10:0] Test register only. Indicates a non-zero
result if read whilst actual slew occurs.
0x000 R
Table 7.23 CORR CHx_CODE_SLEW Register
7.6.19 CHx_EPOCH_CHECK Register - Read Address Offset <CHx_Control> + 0x1C
This register address gives the instantaneous value of the CHx_1MS_EPOCH and the CHx_20MS_EPOCH
counters. It can be used to verify if the software has properly initialised the Epoch counters. Its value is not latched
and is incremented on each DUMP. To ensure the correct result, this register should be read only when there is no
possibility of getting a DUMP during the read cycle, by synchronising the read to NEW_ACCUM_DATA.