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13: Real Time Clock
GP4020 GPS Baseband Processor Design Manual 133
Bit
No.
Mnemonic Description Reset
Value
R/W
15:1 RTC_PRE[15:1]
Number of RTC clock cycles at sample time, within 1 second since last
divider reset/rollover. (One clock cycle = 1/32768 = 30.5
µs).
Most Significant Bit = Bit 15.
Note: This data ONLY reset by writing ‘0’ to bit 0 of this register. NOT
resettable by any other reset source.
0x0000 R
0 RTC_RESB Write '0': Reset RTC Counter and divider
Write '1': No effect
Read: Always read '0'
0R/W
Table 13.2 RTC_PRE Register
13.3.2 RTC Accumulated Seconds - 16 LSBs - RTC_SEC_B - Memory Offset 0x002
Readable only. A read of this register returns the least significant 16-bits of the accumulated RTC seconds in the
24-bit second counter, at the time of access, upto a value of 2
24
seconds = 16.7Mseconds = 194days. The counter
will stop counting when all 24-bits are set to ‘1’. At the time this register is accessed, the values in register
RTC_SEC_T (part of Register COMPS_RTCS) will be latched.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:0 RTC_SEC_B 16 LSBs of accumulated RTC seconds since last 24-bit counter reset.
Most Significant Bit = Bit 15
Note: This data ONLY reset by writing ‘0’ to bit 0 of RTC_PRE.
NOT resettable by any other reset source.
0x0000 R
Table 13.3 RTC_SEC_B Register
13.3.3 RTC Pre-Scaler Comparison Register - COMP_RTCP - Memory Offset 0x004
This is a Read / Write register used to set a Comparison value (15-bits) which is compared with the accumulated
value in the 15-bit RTC Pre-scaler by means of a comparator block. When the value in the comparison register and
the RTC Pre-scaler are equal, and the values in the COMP_RTCS register equals the 8 LSBs of the RTC Counter,
an Interrupt signal RTC_CMP_INT is produced. The comparator is disabled during a write to this register.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:1 COMP_RTCP[15:1] 15-bit RTC Pre-scaler Comparison Value.
Most Significant Bit = Bit 15.
0x7FFF R/W
0 COMP_RTCP[0] Read: Always read '0' 0 R
Table 13.4 RTC COMP_RTCP Register
13.3.4 RTC Second Comparison Register - COMP_RTCS - Memory Offset 0x006
This is a dual-purpose register.
The Read Register [15:8] holds RTC_SEC_T[7:0]; the latched value of the 8 MSBs of the accumulated RTC
seconds in the 24-bit second counter, at the time of access, upto a value of 2
24
seconds = 16.7Mseconds =
194days. The counter will stop counting when all 24-bits are set to '1'.
The Read / Write register [7:0] is used to set a Comparison value (8-bits) which is compared with the accumulated
value in the 8 LSBs of the RTC Second Counter by means of a comparator block. When the value in the
comparison register and the RTC Second Counter are equal, and the values in the COMP_RTCP register equals
the 15-bits of the RTC Pre-scaler, an Interrupt signal RTC_CMP_INT is produced. The comparator is disabled
during a write to this register.