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7: 12-Channel Correlator
GP4020 GPS Baseband Processor Design Manual 63
1. reading at TIC 0 : CHx_CARR_DCO_PHASE 0 = PH 0
2. reading at TIC 1 : CHx_CARR_DCO_PHASE 1 = PH 1
CHx_CARR_CYCLE 1 = K 1 + 1
3. reading at TIC
2 : CHx_CARR_DCO_PHASE 2 = PH 2
CHx_CARR_CYCLE 2 = K 2 + 1
×=
++=
++×=∆
+
−
2
) (2
) (2 2
01
1024
CO_PHASECHx_CARR_DCO_PHASECHx_CARR_D
YCLECHx_CARR_C
PH PH1K
PHPHKY
10
1
101
11
π
π
π
π
∑∑
+
−
×=∆Υ
=
1024
CO_PHASECHx_CARR_DCO_PHASECHx_CARR_D
YCLECHx_CARR_C
last0
last
1
2
i
π
Note: The
Carrier Cycle Counter value is stored at every TIC and the Counter is reset
Figure 7.4 Integrated carrier phase
7.5 12 Channel Correlator Interface Timing
In addition to the detailed timings associated with individual read and write cycles, the internal architecture of the
correlator also imposes limits on cycle to cycle timings (in particular write to write cycle and write to read cycle).
In the GP4020, it must be ensured that no attempts are made to access the 12-channel correlator for the 300ns
following the end of a correlator write cycle. However, if the controlling software is to be allowed to write rapidly to
the correlator (e.g. block writes), then a more complex bus interface (which inserts wait states) will be required.
Note that this limitation only applies after correlator writes, and does not apply to writes to the correlator
X_DCO_INCR_HIGH address.
The correlator section of the GP4020 uses a multi–phase clock internally, and the correlator registers load on
specific clock phases. At the end of a write cycle, the falling edge of the internal write strobe latches both the
relevant address and data bits. This data is then loaded from the internal data bus to the relevant register at some
time during the following 300ns. A write cycle to the Correlator with no writes in the preceding 300ns (314ns), may
be performed immediately, so long as the detailed signal timings are met. However, subsequent read or write
cycles to the Correlator after this write cycle may need to be delayed if they would modify the internal address or
data lines. Correlator read cycles with no write cycles in the preceding 300ns (314ns) are self–contained, and do
not delay subsequent cycles. An isolated read cycle requires only sufficient wait states to meet the detailed signal
timings.