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6: BSIO Interface
42 GP4020 GPS Baseband Processor Design Manual
When the Sequencer asserts CWORD_EN, the Control Word is shifted out at SDO prior to any data to be written
from the FIFO. CWORD_WR will be set when a Control Word is written to the Control Word Register, and will be
cleared at the end of an Operation. When in Page Mode, it will set the OPERATION bit in the Status Register.
6.7 BSIO Read Buffer
The Read Buffer consists of a Receive shift register, two 32-bit receive FIFOs and Control Logic as shown in Figure
6.10 below.
BuILD Bus
FIFO
2 X 32 bits
TRFORMAT
SHIFT_RX
END_OF_RX
READERR
RDREADY
RXWORD
SELBYTE
SDI
RX_CLK
32 BIT BUS
RECEIVE
SHIFT
REGISTER
RX_CLK
Figure 6.10 BSIO Read Buffer
Received data is shifted into the Receive shift register serially, and transferred to the FIFO in word / byte format,
from where it may be read as a 32-bit word. Note that like the Write Buffer, not all 32-bits in the Read FIFO will
necessarily be valid. When the SELBYTE bit in the Transfer Register selects byte mode, each 32-bit word is made
up of four consecutive bytes. However in non-byte mode, the RXWORD bits in the Transfer Register set the width
of the word that is to be received. Hence, the higher order bits that do not make up the word are redundant. For
example if a 20-bit Word were to be selected, then bdata<19:0> would make up the word, with bdata<31:20> not
being used.
Incoming serial data at SDI is shifted into the shift register by RX_CLK and the control signal SHIFT_RX both
generated by the Sequencer. Once the number of valid bits that make up a 32-bit word have been transferred into
the FIFO, an END_OF_RX signal generated by the Sequencer will set the RDREADY bit in the Status Register.
The RDREADY bit is cleared when the Read FIFO is empty.
As the FIFO is capable of storing two 32-bit words, it is possible to store the next word before the previous one has
been read.
If however a third word/byte were to be completely received whilst the FIFO is full the READERR bit in the Status
Register will be set, and further data will not be stored until the first word is read. READERR is cleared by a read of
the Status Register.
The TRFORMAT bits in the Slave Select Registers select between MSB and LSB formats, for each of the six slave
devices. Note that in byte mode bit 7 of each byte would be the MSB, whereas in Word mode this would be its most
significant bit.
6.8 BSIO Sequencer
The Sequencer consists of Read/Write Counters and Control logic as shown in Figure 6.11 below.