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15: 1PPS Timemark Generator
156 GP4020 GPS Baseband Processor Design Manual
TIC_INT_EN[1:0] = '01'. Indicates that the TIC period will automatically be corrected independently of GPS
software each time the phase_counter reaches 7, by means of the RELOAD_TIC signal. Each TIC event triggers a
new phase_offset calculation. When the new phase_offset calculation is complete, TIC_INT is set (even if TIC
period correction is not required). The ADJ_TIC_RD bit indicates if the next TIC period will be extended. Writing to
ADJ_TIC has no effect. TIC_INT and ADJ_TIC_RD are used to indicate to the software which TIC periods are
being extended.
TIMEMARK will automatically be maintained at approximately 1PPS (TIC_INT and ADJ_TIC_RD are used to
indicate to the software which TIC periods are being extended).
TIC_INT_EN[1:0] = 10. Allows the TIC period extension decision to be taken away from Hardware, and allows the
decision of whether to extend the TIC period (by means of RELOAD_TIC) to be influenced by software. In this
case, TIC_INT is set before a TIC extension is required, as the result of a phase_offset calculation overflow.
If a new phase_offset is calculated, and the result indicates the next TIC period should be extended, both the
ADJ_TIC_RD bit and the TIC_INT interrupt signal will be set to '1'. A write ADJ_TIC_WR of '1' will cause the next
TIC period to be extended. It will also cause clear ADJ_TIC_RD. (Writing '0' to ADJ_TIC_WR has no effect).
If '1' is not written to ADJ_TIC_WR, the next TIC period will not be extended. Any TIC period can be extended (by
writing '1' to ADJ_TIC_WR), irrespective of the state of ADJ_TIC_RD.
To maintain TIMEMARK at approximately 1PPS, '1' should be written to ADJ_TIC_WR after every TIC_INT
interrupt.
TIC_INT_EN[1:0] = 11. Allows the TIC period extension decision to be taken away from Hardware, and allows the
decision of whether to extend the TIC period (by means of RELOAD_TIC) to be influenced by software. In this
case, TIC_INT is set after every phase_offset calculation regardless of whether or not TIC period extension is
required (i.e. independent of adder overflow.)
Because of TIC_INT, the ADJ_TIC_RD bit needs to be read to find out if the next TIC period needs to be extended.
If ADJ_TIC_RD is set, '1' should be written to ADJ_TIC_WR to extend the next TIC period. (Writing '0' to
ADJ_TIC_WR has no effect, if '1' is not written to ADJ_TIC_WR, TIC period will not be extended).
Any TIC period can be extended (by writing '1' to ADJ_TIC_WR), irrespective of the state of ADJ_TIC_RD. To
maintain TIMEMARK at approximately 1PPS, at every TIC_INT interrupt, ADJ_TIC_RD should be read, and if it is
set, '1' should be written to ADJ_TIC_WR.
The reset condition for the 1PPS Timemark Generator is for TIC_CORR to equal '000', and TIC_INT_EN to equal
'00'. If it is left in this condition, the only observable difference to the TIC and TIMEMARK behaviour (between
GP4020 and GP2021) is the additional half M_CLK cycle delay on TIMEMARK output.
15.4.3 Timemark setting example 1; TIC period Slewing with No Receiver Clock Offset
It is assumed that the Receiver Clock Reference (i.e. TCXO for RF Front-end) has a zero offset. To automatically
correct the timing of 10 cycles of TIC for each Timemark output pulse from 999999µs to 1.000000s, the 1PPS
Timemark generator needs to add a 1µs delay to the Timemark output. The default TIC period would need to be set
to 99999.9µs, (PROG_TIC_HIGH + PROG_TIC_LOW would be set with 0x08B823). TIC_INT_EN[1:0] would be
set to '01', and TIC_CORR would be set to '100' (four M_CLK cycles = 100ns). On the first TIC event, Phase_offset
would increase to 4 (which would have no affect on correlator core). If TIMEMARK were generated, it would be
delayed by the last Phase_Offset (i.e. 0). On the next TIC event, 'Phase_offset' would change to 1 and
RELOAD_TIC would be set (delaying the next TIC event by one cycle of 175ns). This process would continue, as
shown in Table 15.1 below. TIC Event 0 is assumed phase-aligned to UTC, so the required delay is 0µs.