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6: BSIO Interface
46 GP4020 GPS Baseband Processor Design Manual
Bit
No.
Mnemonic Description Reset
Value
R/W
9:0 RDSIZE
Read Size. When written configures the number of bytes/words to be read
in the current operation.
With RDSIZE = 0000000000 for bytes/words = 0 to RDSIZE =
1111111111 for bytes/words = 1023
00000
00000
W
RDREM Read Remaining. When read returns number of bytes/ words remaining to
be received in the current operation.
00000
00000
R
Table 6.4 BSIO Transfer Register
6.9.3
BSIO Mode Register - MODE - Memory Offset 0x0008
Bit
No.
Mnemonic Description
Reset
Value
R/W
31:6
Reserved
All = 0 R
5 CWORDSEL Control Word Select: When High selects Page mode,
when Low selects Standard mode.
0R/W
4:0 CWORD
Control Word Width: These bits configure the width of the
Control Word between 2-bits and 32-bits.
CWORD = 00000 or 00001 selects a width of 2, whilst
CWORD = 11111 selects a width of 32.
11111 R/W
Table 6.5 BSIO Mode Register
6.9.4
BSIO Slave Select Registers - SLAVE0, SLAVE1 - Memory Offset (SLAVE0 = 0x0010, SLAVE1
= 0x0014)
Bit
No.
Mnemonic Description Reset
Value
R/W
31:6
Reserved
All = 0 R
5 TRFORMAT Transfer Format. A High selects MSB as the first bit, with a Low selecting
LSB.
0R/W
4CYCDELAY
Cycle Delay. Allows the insertion of a 1-cycle delay, between write and read
cycles. A High selects a delay and a LOW no delay.
0R/W
3 CPOL Clock Polarity. When Low, the SCLK idle state is Low, when High the SCLK
idle state is High. Note that if two Slaves have different idle states, then the
start of an operation can be delayed as required.
0R/W
2WRPOL
Write Polarity. This bit selects either a rising or falling edge of SCLK for write
cycles. A High selects a Rising edge, with a Low selecting a Falling edge.
The edge is with respect to the BSIO block, not the slave. Hence WRPOL
selecting a rising edge configures the BSIO to generate output data
transitions on the rising edge of SCLK, to be latched by the current slave on
the falling edge.
0R/W
1 RDPOL
Read Polarity. This bit selects either a rising or falling edge of SCLK for read
cycles. A High selects a Rising edge, with a Low selecting a Falling edge.
The edge is with respect to the BSIO block, not the slave. Hence RDPOL
selecting a rising edge configures the BSIO to register input data on the
rising edge of SCLK, which has been generated by the current slave on the
falling edge.
0R/W
0 ENPOL Enable Polarity. Sets the polarity of the Slave Select output as either active
Low or active High.
A Low configures the corresponding output as active Low, with a High
configuring it as active High.
0R/W
Table 6.6 BSIO Slave Select Register