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1: Introduction
4 GP4020 GPS Baseband Processor Design Manual
Details can be found in section 6 "B
µ
ILD SERIAL INPUT OUTPUT (BSIO) INTERFACE" on page 33.
1.3.5 12 Channel Correlator (CORR)
This module contains 12 channels of PRN code correlators for spread-spectrum correlation of 12 simultaneous
signals. Each channel contains an independent carrier DCO to allow independent mix down of a satellite signal to
base-band before code correlation occurs. The correlator is designed to extract data modulated at a nominal
chipping-rate of 1.023MBPS, and can be used on both Navstar C/A code GPS signals, and Inmarsat WAAS codes.
Details can be found in section 7 "12-CHANNEL CORRELATOR (CORR)" on page 49.
1.3.6 DMA Controller (DMAC)
Two DMA engines are available on the micro-controller. These are configured as a pair to provide a memory-to-
memory DMA capability between UART1, UART2 and any location in the ARM7TDMI memory space. Alternatively,
they may be used independently for fly-by transfers between the UARTs and either on-chip or off-chip locations.
Single or multiple byte transfers (Demand or Burst Mode) are supported and may be word, half-word or byte wide.
Details can be found in section 8 "DMA CONTROLLER (DMAC)" on page 91.
1.3.7 Embedded Micro-Controller Debug Options
The Firefly MF1 Core incorporates three sophisticated methods of hardware and software debug. The options are:
• EmbeddedICE accessed via the ARM7TDMI JTAG interface.
• Angel Debug Monitor.
• Logic Analyser coupled with an Inverse Assembler accessed via the SSM debug interface.
The GP4020 can use any of these options, but special emphasis has been placed on the EmbeddedICE and Logic
Analyser options. The JTAG and SSM debug interfaces are multiplexed onto the same pins, and can be selected
by setting the NICE (pin 84) to High for SSM, or Low for JTAG.
1.3.8 Firefly MF1 Micro-Controller core
The Firefly MF1 Micro-controller is an Embedded Micro-controller core developed by Zarlink Semiconductor. It
combines the processing power of the ARM7TDMI microprocessor with a number of peripheral components:
• Direct Memory Access Controller (DMAC)
• Interrupt Controller (INTC)
• Memory Peripheral Controller (MPC), incorporating Up-Integration Module (UIM)
• System Services Module (SSM)
• System Timer/Counter (SYSTIC)
• Universal Asynchronous Receiver / Transmitter (UART)
Details can be found in the Firefly MF1 Core Design Manual, (DM5003), also available from Zarlink Semiconductor.