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12: Peripheral Control Logic
116 GP4020 GPS Baseband Processor Design Manual
RF_PLL_LOCK
NRESET
UART_CLK
3 CYCLES
Any Freq
Figure 12.3 RF_PLL_LOCK Hardware Reset Generation
POWER_GOOD
NRESET
UART_CLK
3 CYCLES
Any Freq
Figure 12.4 POWER_GOOD Hardware Reset Generation when POWG_EN = '0', and UART_CLK NOT
derived from an RF Front-end.
POWER_GOOD
RF_PLL_LOCK
NRESET
UART_CLK
3 CYCLES - 150ns
20MHz
Any Freq
CLKI / CLKT
UNDEFINED
5ms
POWER DOWN
MODE
Figure 12.5 POWER_GOOD Hardware Reset Generation when POWG_EN = '1'. Assumes that power to RF
Front-end fails, and RF_PLL_LOCK is low for upto 5ms after power-up.