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8: DMA Controller
94 GP4020 GPS Baseband Processor Design Manual
3.4) Set the DMAC Base Transfer Count Register (BTR), to indicate to the DMAC how many transfers are
required in the DMA operation being programmed. In the case of the Packet transfer being defined here,
this number is the (number of data bytes - 1), of Packet size "1" which are required to be transferred from
memory to the UART 1 or 2 transmit port. So if the transfer is to be for 10,000 8-bit bytes, the setting
for this register should be "10,000 - 1" = "9,999" = 0x270F.
4) Once all the DMAC features have been programmed:
4.1) Set to ”1” the Transmit Interrupt Enable bit (bit 5) of the UART 1 (or 2) Serial Control Register (CR) to
enable interrupts generated when the UART Transmit register is empty. This is vital when using UART2
with hardware DMAC triggers from UART2, to ensure that the DMAC is triggered correctly (refer to
Section 8.3 "DMAC Triggering" on page 99).
4.2) Set to "1" the DMAC Channel Status bit (bit 0) in the Channel 1 (or 2) Control and Status Register (CSR),
to allow the DMA transfer to be triggered as defined in step 2) above. This action should be done
independently of any other settings to the Control and Status Register in order to avoid setting and
triggering errors.
Note: A write of a bit to the DMAC CSR register involves writing a byte, half-word or word. It is worth ensuring
that the settings already programmed into the CSR are not corrupted when setting bit 0 to "1", by re-
writing the values of all the other bits in the register to those defined above.
Refer to Section 8.3 "DMAC Triggering" on page 99 for information of how both Software and Hardware triggering
operates with a DMA transfer.