Arm Enterprises GP4020 GPS Receiver User Manual


 
7: 12-Channel Correlator
GP4020 GPS Baseband Processor Design Manual 77
Bit
No.
Mnemonic Description Reset
Value
R/W
15:14
Not used
'0' when read. - R
13:8 CHx_20MS_EPOCH[5:0] Instantaneous value of the CHx_20MS_EPOCH.
Valid range = 0 to 49
0x00 R
7:5
Not used
'0' when read. - R
4:0 CHx_1MS_EPOCH[4:0] Instantaneous value of the CHx_1MS_EPOCH
Valid range = 0 to 19
0x00 R
Table 7.24 CORR CHx_EPOCH_CHECK Register
7.6.20 CHx_EPOCH Register - Read Address Offset <CHx_Control> + 0x10
This register gives the values of the CHx_1MS_EPOCH and the CHx_20MS_EPOCH counters, which were latched
at the last TIC event.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:14
Not used
'0' when read. - R
13:8 CHx_20MS_EPOCH[5:0] Value of the CHx_20MS_EPOCH counter,
sampled at the last TIC event.
Valid range = 0 to 49
0x00 R
7:5
Not used
'0' when read. - R
4:0 CHx_1MS_EPOCH[4:0]
Value of the CHx_1MS_EPOCH counter,
sampled at the last TIC event.
Valid range = 0 to 19
0x00 R
Table 7.25 CORR CHx_EPOCH Register
7.6.21
CHx_EPOCH_COUNT_LOAD Register - Write Offset <CHx_Control> + 0x1C
MULTI_EPOCH_COUNT_LOAD Register - Write Address Offset 0x180 + 0x1C
ALL_EPOCH_COUNT_LOAD Register - Write Address Offset 0x1C0 + 0x1C
This register is used to load the EPOCH counters with values that can synchronise them with the GPS Data
message from a GPS satellite. The 20ms EPOCH Counter together with the 1ms EPOCH Counter covers a range
from 0ms to 999ms. The execution of the transfer of data from this register to the EPOCH counters is determined
by the current channel mode: PRESET or UPDATE.
In UPDATE mode, the data written into these registers is immediately transferred to the 1 ms and 20 ms epoch
counters.
In PRESET mode however, the data is transferred only after the next TIC. It is important to load the CHx_EPOCH
register last in the PRESET mode loading sequence because the trailing edge of a write to this register enables the
whole PRESET operation on the next TIC. Refer to the description of PRESET mode in Section 7.4.9 on page 61.
Bit
No.
Mnemonic Description
Reset
Value
R/W
15:14
Not used
-W
13:8 CHx_20MS_EPOCH[5:0] Value to be loaded into the
CHx_20MS_EPOCH counter.
Valid range = 0 to 49
0x00 W
7:5
Not used
-W
4:0 CHx_1MS_EPOCH[4:0] Value to be loaded into the
CHx_1MS_EPOCH counter. Valid
range = 0 to 19
0x00 W