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14: System Clock Generator
GP4020 GPS Baseband Processor Design Manual 135
14 SYSTEM CLOCK GENERATOR (SCG)
14.1 Introduction
The System Clock Generator (SCG) is used to generate two clock signals for the GP4020:
• The UART_CLK which runs UART2 continuously and produces the BµILD Clock. The BµILD Clock runs all the
BµILD bus components, including the Firefly MF1 core with the ARM7TDMI microprocessor via a disable gate
in the Peripheral Control Logic Block.
• The Correlator Master Clock (M_CLK).
The UART_CLK is used to generate the microprocessor system clock. It can be derived from two sources (RF
Front end or a Processor Crystal Oscillator) and the frequency can be programmed to suit the overall system
requirements, with the use of an on-chip PLL.
The M_CLK is essentially a 40MHz clock, which is phase-locked to the RF Front-end. The CLK_T and CLK_I
signals from the RF Front-end are used to provide M_CLK in conjunction with a differential input amplifier. The
M_CLK cannot be derived from any other source.
Figure 14.1 below shows a block diagram of the System Clock Generator.
DIV 2
DIV 2
CLK_T
CLK_I
UART_CLK
(to PCL)
PR_XIN
PR_XOUT
PRX_PDOWN
RF_PDOWN
M_CLK
(to Correlator)
PLL_IN_SEL[1:0]
PLL
CLKINB
CLKOUTB
CLKFBKB
ENB
PD
DIV [4:0]
AT1
DT1
CHP [4:0]
SG1
TM1
TM2
VCOD [1:0]
ENB
220k
ENBO
IDDQ_TEST
SG1
TM1
TM2
FROM
RF
FRONT
END
PROCESSOR
CRYSTAL OSCILLATOR
- 10.0 TO 16.0 MHz
40MHz LOW LEVEL
DIFFERENTIAL INPUT
PLLAT1
PLLDT1
20.0MHz
10.0MHz
10.0 to 16.0MHz
40.0MHz
FROM
EXTERNAL
CRYSTAL
PLL_CNTL
REGISTER
UIM ADDRESS & DATA BUS UIM BUS
SYNCEN
PRX_PDOWN
PLL_IN_SEL [1:0]
PLL_BYP
B_CLK_SEL [1:0]
PLL_ENABLE
RF_PDOWN
SYNCEN
DIV[4:0]
CHP[4:0]
VCOD[1:0]
SG1
TM1
TM2
VCOD[1:0]
DIV[4:0]
CHP[4:0]
SYNCEN
UART_CLK
Divider
(Div
1 / 2 / 4 / 8)
B_CLK_SEL[1:0]PLL_BYP
POWER
CONTROL
LINES FROM
PCL
NPOR_RESET
PLL_PDOWN
TEST
TESTTEST
PLL_PDOWN
PLL_ENABLE
IDDQ_TEST IDDQ_TEST
ENB
IDDQ_TEST
IDDQ_TEST
Figure 14.1 System Clock Generator Block Diagram
The System Clock Generator features two input sources:
• 40MHz low-level differential clock signal from an RF Front-end
• Processor Crystal Oscillator, for crystal frequencies between 10.0MHz and 16.0MHz.