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7: 12-Channel Correlator
72 GP4020 GPS Baseband Processor Design Manual
7.6.10 CHx_CARRIER_DCO_INCR_HIGH Register - Offset <CHx_Control> + 0x0C
MULTI_CARRIER_DCO_INCR_HIGH Register - Offset 0x180 + 0x0C
ALL_CARRIER_DCO_INCR_HIGH Register - Offset 0x1C0 + 0x0C
The _CARRIER_DCO_INCR_HIGH Register contains the 10 Most Significant bits of a 26-bit value used to set the
frequency of the Carrier DCO in the correlator channel selected. The programmed value is treated as an increment
of a Minimum frequency step.
The contents of registers _CARRIER_DCO_INCR_HIGH and _CARRIER_DCO_INCR_LOW are combined to form
the 26-bits of the CHx_CARRIER_DCO_INCR register, the carrier DCO phase increment number. In order to write
successfully, the top 10-bits must be written first, to any of the _HIGH addresses. They will be stored in a buffer and
only be transferred into the increment register of the DCO together with the _LOW word.
A 26-bit increment number is adequate for a 27-bit accumulator DCO, as the increment to the MSB is always zero.
The LSB of the INCR register represents a step given by:
Min Step Frequency = (40MHz / 7) / 2
27
= 42.57475mHz
Output Frequency = CHx_CARRIER_DCO_INCR * Min Step Frequency.
With a GP2015/GP2010 style front end, the nominal value of the IF is 1.405396826 MHz before allowing for
Doppler shift or crystal error. Writing 0x01F7 B1B9 into the CHx_CARRIER_DCO_INCR register will generate a
local oscillator frequency of 1.405396845 MHz.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:10
Not used
-W
9:0 CHx_CARRIER_DCO_INCR [25:16] Bits 25:16 of the 26-bit Carrier DCO Increment Register.
Must be written before CHx_CARRIER_DCO_INCR_LOW
values.
0x000 W
Table 7.13 CORR CHx_CARRIER_DCO_INCR_HIGH Register
7.6.11 CHx_CARRIER_DCO_INCR_LOW Register - Offset <CHx_Control> + 0x10
MULTI_CARRIER_DCO_INCR_LOW Register - Offset 0x180 + 0x10
ALL_CARRIER_DCO_INCR_LOW Register - Offset 0x1C0 + 0x10
This register contains the 16 least significant bits for the CHx_CARRIER_DCO_INCR register. Refer to
"CHx_CARRIER_DCO_INCR_HIGH" for more information.
Bit No. Mnemonic Description Reset
Value
R/W
15:0 CHx_CARRIER_DCO_INCR [15:0] Bits 15:0 of the 26-bit Carrier DCO Increment Register 0x0000 W
Table 7.14 CORR CHx_CARRIER_DCO_INCR_LOW Register
7.6.12 CHx_CARRIER_DCO_PHASE - Read Address Offset <CHx_Control> + 0x0C
This register contains the 10-bits of the Carrier DCO phase accumulator, and indicates the phase of a carrier DCO
cycle, as a 10-bit sub-multiple of one DCO carrier cycle, as sampled at the last TIC. The weight of the least
significant bit is 2π / 1024 radians of a Carrier DCO cycle. These bits form an unsigned integer valid from 0 to 1023.
CHx_CARRIER_DCO_PHASE provides sub-cycle phase-measurement information and so complements the
information given by CHx_CARRIER_CYCLE_HIGH and _LOW.
The register value is latched on each TIC and is not protected by any overwrite protection mechanism.