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7: 12-Channel Correlator
GP4020 GPS Baseband Processor Design Manual 73
Bit
No.
Mnemonic Description Reset
Value
R/W
15:10
Not used
'0' when read 0 R
9:0 CHx_CARRIER_DCO_PHASE [9:0] Bits 9:0 of the 10-bit Carrier DCO Phase Count. 0x000 R
Table 7.15 CORR CHx_CARRIER_DCO_PHASE Register
7.6.13 CHx_CODE_DCO_INCR_HIGH Register - Offset <CHx_Control> + 0x14
MULTI_CODE_DCO_INCR_HIGH Register - Offset 0x180 + 0x14
ALL_CODE_DCO_INCR_HIGH Register - Offset 0x1C0 + 0x14
The _CODE_DCO_INCR_HIGH Register contains the nine Most Significant bits of a 25-bit value used to set the
frequency of the Code DCO in the correlator channel selected. The programmed value is treated as an increment
of a Minimum frequency step.
The contents of registers _INCR_HIGH and _INCR_LOW are combined to form the 25-bits of the
CHx_CODE_DCO_INCR register, the Code DCO phase increment number. In order to write successfully, the top
9-bits must be written first, to any of the _HIGH addresses. They will be stored in a buffer and only be transferred
into the increment register of the DCO together with the _LOW word. A 25-bit increment number is adequate for a
26-bit accumulator DCO as the increment to the MSB is always zero.
The LSB of the INCR register represents a step given by:
Min Step Frequency = (40MHz / 7)/2
26
= 85.14949mHz
Output Frequency = CHx_CODE_DCO_INCR * Min Step Frequency.
Note: The Code DCO drives the Code Generator to give half chip time steps and so must be programmed to twice
the required chip rate. This means that the chip rate resolution is 42·57475mHz. The nominal frequency is
1.023000000 MHz before allowing for Doppler shift or crystal error. Writing 0x016E A4A8 into the
CHx_CODE_DCO_INCR register will generate a chip rate of 1.022999968 MHz.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:9
Not used
-W
8:0 CHx_CODE_DCO_INCR [24:16] Bits 24:16 of the 25-bit Carrier DCO Increment Register.
Must be written before CHx_CODE_DCO_INCR_LOW
values.
0x000 W
Table 7.16 CORR CHx_CODE_DCO_INCR_HIGH Register