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8: DMA Controller
GP4020 GPS Baseband Processor Design Manual 101
8.4 Cautionary Notes
8.4.1 Packet Transfers in place of Block Transfers
For Both Single-addressed and Dual-addressed transfers using the GP4020 DMA, it is NOT recommended to use
DMA Block-transfers, but to use Packet transfers instead.
Packet transfers allow the ARM to have access to the BµILD bus potentially on alternate clock cycles. When a
Block transfer is initiated, the DMAC occupies the BµILD bus continuously for the period it takes to transfer the
whole block of data defined by the contents of the Base Transfer Count Register in the DMA. In a GPS receiver, the
RTOS running on the ARM microprocessor needs to access the 12-channel correlator to service ACCUM_INT
interrupts, once every 500us or so. A DMA block transfer may prevent the ARM from accessing the correlator in
this time-critical activity, and the GPS function may fail consequently.
8.4.2 ARM FIQ Promotion
The ARM7TDMI has the lowest priority on the GP4020 BµILD bus, under the DMA and SSM blocks (refer to
Section 2.5 in the Firefly MF1 Core Design Manual (DM5003) for more information). When the DMAC is
undertaking a data transfer, the DMAC has priority over the ARM7TDMI.
It is NOT recommended to prioritise the ARM7TDMI over the DMAC during a DMA transfer when the ARM receives
a FIQ interrupt, although a mechanism exists for this. This is achieved by setting to "1" the "Bus Arbitration Bit" (bit
1) of the System Configuration Register in the Firefly SSM, to enable ARM FIQ promotion (refer to Table 2-5 in the
Firefly MF1 Core Design Manual (DM5003)). Problems arise in the DMA, when the DMAC is interrupted from its
transfer, and it can cause the DMAC functions to crash when the BµILD bus is handed back to it.
Further details for the programming of the DMAC Controller can be found in Section 6 of the "Firefly MF1 Core
Design Manual" DM5003, available from Zarlink Semiconductor.