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7: 12-Channel Correlator
78 GP4020 GPS Baseband Processor Design Manual
Table 7.26 CORR CHx_EPOCH_COUNT_LOAD Register
7.6.22 CHx_I_TRACK Register - Read Address Offset <CHx_Accumulate> + 0x00
CHx_Q_TRACK Register - Read Address Offset <CHx_Accumulate> + 0x04
CHx_I_PROMPT Register - Read Address Offset <CHx_Accumulate> + 0x08
CHx_Q_PROMPT Register - Read Address Offset <CHx_Accumulate> + 0x0C
These registers hold the Accumulated Data values which result from Code mixing, which are used on each DUMP
to store the 16–bit Integrate–and–Dump accumulator results. The values contained in the registers are 2’s
complement values with the valid range of the data from –2
15
to +(2
15
–1).
These registers are read–only registers, which can be read at any time. Their content is not protected by any
overwrite protection mechanism, so the set of four registers must be read soon after an ACCUM_INT to be sure
that newer data will not cause an overwrite part way through the set. The CHx_I_PROMPT and CHx_Q_PROMPT
contain the Accumulated Data from the Prompt arm. The CHx_I_TRACK and CHx_Q_TRACK contain the
Accumulated Data from the Tracking arm.
To track satellites correctly, only data read with the CHx_NEW_ACCUM_DATA bit set High should be used. An
overflow or underflow condition cannot be reached.
Bit
No.
Mnemonic Description Reset
Value
R/W
15:0 CHx_I_TRACK[15:0]
CHx_Q_TRACK[15:0]
CHx_I_PROMPT[15:0]
CHx_Q_PROMPT[15:0]
Bits 15:0 of the 16-bit Integrate and Dump
accumulator in either I or Q parts of either
Track or Prompt correlator arms
0x0000 R
Table 7.27 CORR CHx_I /_Q_TRACK/_PROMPT Register
7.6.23 CHx_SATCNTL Register - Write Address Offset <CHx_Control> + 0x00
MULTI_ SATCNTL Register - Write Address Offset 180 + 0x00
ALL_SATCNTL Register - Write Address Offset 1C0 + 0x00
The SATCNTL Register is used to set up a correlator channel to generate a particular code from the code-
generator. It also is used to set-up either PRESET or UPDATE mode, and to select either SIGN0/MAG0 or
SIGN1/MAG1 inputs from a RF Front-end (this feature not available on the 100-pin version of GP4020!).
CHx_SATCNTL is a write–only register that can be written into at any time. Any modification to the content is
effective at the next DUMP in UPDATE mode or at the next TIC in PRESET mode for all bits, apart from PRESET
UPDATEB, which defines whether a channel is in PRESET or UPDATE mode. It is important to program this
register first when starting the initialisation of a PRESET sequence to get the channel into PRESET mode, or the
other write operations will act too soon.
When TRACK_SEL[1:0] selects the dithering code, the Tracking arm will use the EARLY code for 20 periods of the
Gold code, the LATE code for the next 20 periods and then this process of alternating between Early and Late code
will be repeated indefinitely. The Tracking Arm will toggle between Early and Late Codes on every increment of a
20ms Epoch Count. Its state can be determined by reading the ACCUM_STATUS_C register.
The output code is a sequence of +1’s and –1’s for all code types except EARLY–MINUS–LATE where the result
can also be a '0'. In EARLY–MINUS–LATE mode the values are not the +2, 0, –2 that results from the calculation
(+1 or –1) – (+1 or –1), but are halved to +1, 0, –1. This must be considered when choosing thresholds in the
software, as the correlation results will be exactly half of the values otherwise expected.
G2_LOAD[9:0] C/A CODE SELECTION: The CHx_SATCNTL register programs the CODE GENERATOR by
setting the G2 register to the appropriate starting pattern to generate the required GPS or INMARSAT–GIC codes.
The G2_LOAD register may be programmed at any time but the value is only used when the code sequence
restarts, at the following DUMP in UPDATE mode, or at the following TIC in PRESET mode. The pattern to load is