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6: BSIO Interface
GP4020 GPS Baseband Processor Design Manual 35
• After all data has been sent, since there is no read data, a read data interrupt is generated immediately. If
reading data, a read interrupt would be generated after each four bytes of data are read and after the last byte
of data is read.
The BSIO consists of six blocks, the Sequencer, Frequency Divider, Write Buffer, Read Buffer, Slave Select Logic
and Interrupt Control. A block diagram for the BSIO is shown in Figure 6.2 below.
Since the BSIO is an external Master, the only operations that are provided are a Read or a Write to a Slave. A
Write operation consists of sending between zero to 1023 bytes/words to a Slave. A Read operation consists of first
optionally sending between 0 to 1023 bytes/words to a Slave, and next receiving 0 to 1023 bytes/words.
The timing for a Read and Write operation from the BSIO to a Slave device is shown in Figure 6.3 and Figure 6.4
below. Refer to “Electrical Characteristics” in the “GP4020 GPS Baseband Processor Datasheet”, DS5134 for
values of these timing parameters.
Note that the clock to the Slave devices SCLK, is static, i.e. held in either the High or Low state, whilst no operation
is in progress.
Either byte or word transfers for write and read cycles are possible, with the word width being configurable between
2-bits and 32-bits. Data currently being transmitted / received is held in a 32-bit shift register. In addition, data that
has been received or is awaiting transmission is held in a pair of 2 x 32-bit FIFOs. When byte transfers are used,
the 32-bit word in the Read/Write buffers is treated as four consecutive bytes. In this case the lower order byte is
transmitted first and is the first byte to be received. If however word transfers are used, then the selected number of
lower order bits will make up the word, with any remaining higher order bits not being used. For example if a 20-bit
Word were to be selected, then bdata<19:0> would make up the word, with bdata<31:20> not being used.