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8: DMA Controller
100 GP4020 GPS Baseband Processor Design Manual
8.3.2 Software Triggering
Software Triggering of a DMAC channel is the normal mode used in Dual-Addressed (Buffered) data transfers.
A Software Trigger is enabled and disabled dependent on the level of bit [2] of the DMAC Channel Control and
Status Register (CSR). This bit can be set to "1" to initiate a DMAC Software Trigger irrespective of whether the
DMA is in Program state (CSR bit zero cleared to "0") or Ready state (CSR bit zero set to "1").
• If the DMAC Channel Status (bit 0) is in Program state (i.e. cleared to "0"), and the Software Request (bit 2) is
set to "1", DMA transfers will begin immediately after the Channel Status is set to Ready (bit "0" set to "1").
• If the DMAC Channel Status (bit 0) is in Ready state (i.e. set to "1"), and the Software Request (bit 2) is set to
"1", DMA transfers will begin immediately.
In both cases, one software trigger will allow the DMAC channel to transfer the number of packets defined in the
Base Transfer Count Register (BTR) through to completion. The Software Request can be terminated by writing "0"
to CSR bit 2.
However, this can only occur if the DMAC channel is configured to undertake a "Packet" transfer, as a block
transfer will give no allocation of the BµILD bus to the ARM7TDMI. Otherwise, when the number of transfers
defined in the Base Transfer Count Register (BTR) has been completed, the DMAC will clear the Software Request
bit (CSR bit 2) to "0".