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GP4020 GPS Baseband Processor Design Manual Index - VII
Table 7.18 CORR CHx_CODE_DCO_PHASE Register .............................................................74
Table 7.19 CORR CHx_CODE_DCO_PRESET_PHASE Register..............................................74
Table 7.20 CORR CHx_CODE_PHASE Register.......................................................................75
Table 7.21 CORR CHx_CODE_PHASE_COUNTER Register ....................................................75
Table 7.22 CORR CHx_CODE_SLEW_COUNTER Register......................................................76
Table 7.23 CORR CHx_CODE_SLEW Register.........................................................................76
Table 7.24 CORR CHx_EPOCH_CHECK Register ....................................................................77
Table 7.25 CORR CHx_EPOCH Register ..................................................................................77
Table 7.26 CORR CHx_EPOCH_COUNT_LOAD Register.........................................................78
Table 7.27 CORR CHx_I /_Q_TRACK/_PROMPT Register........................................................78
Table 7.28 G2 LOAD settings required for C/A code generator, for valid PRN Numbers ..............79
Table 7.29 CORR CHx_SATCNTL Register...............................................................................80
Table 7.30 CORR MEAS_STATUS_A Register..........................................................................81
Table 7.31 CORR MULTI_CHANNEL_SELECT Register...........................................................82
Table 7.32 CORR PROG_ACCUM_INT Register.......................................................................82
Table 7.33 CORR PROG_TIC_HIGH Register...........................................................................83
Table 7.34 CORR PROG_TIC_LOW Register............................................................................83
Table 7.35 CORR RESET_CONTROL Register.........................................................................84
Table 7.36 CORR STATUS Register .........................................................................................85
Table 7.37 CORR SYSTEM_SETUP Register ...........................................................................86
Table 7.38 CORR TEST_CONTROL Register ...........................................................................87
Table 7.39 CORR TIMEMARK_CONTROL Register ..................................................................89
Table 8.1 Hardware Trigger Source selection for DMAC Channel 1............................................92
Table 9.1 GPIO B_ERROR signal ...........................................................................................105
Table 9.2 GPIO Register Map..................................................................................................105
Table 9.3 GPIO_DIR Register .................................................................................................105
Table 9.4 GPIO_INPUT Register.............................................................................................106
Table 9.5 GPIO_OUTPUT Register.........................................................................................106
Table 10.1 Interrupt Vector Summary ......................................................................................107
Table 10.2 GP4020 Interrupt Sources......................................................................................108
Table 11.1 External Memory Bus Pinout ..................................................................................109
Table 11.2 Memory Peripheral Controller Configuration Registers ............................................109
Table 12.1 DISCIO pin signal multiplex options........................................................................120
Table 12.2 MULTI_FNIO pin signal multiplex options ...............................................................120
Table 12.3 GPIO pin signal multiplex options ...........................................................................121
Table 12.4 Peripheral Control Logic Register Map....................................................................125
Table 12.5 PCL POW_CNTL Register .....................................................................................126
Table 12.6 PCL IO_REV Register............................................................................................127
Table 12.7 PCL IP_READ Register..........................................................................................128