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6: BSIO Interface
GP4020 GPS Baseband Processor Design Manual 37
N
SCLK
SLAVE
DATA IN
SLAVE
DATA OUT
SS0 - SS1
High Z
1 2 3 4 N
TSERCDC
TSERDOD
(N-5)SCLK
TSERCEC
1 2 3 4
(X-5)SCLK
X
TSERSU
TSERHD
Note: Last SCLK cycle shown for reference only - not actually generated in BSIO
Figure 6.3 BSIO Read Operation Timing Diagram
N
SCLK
SLAVE
DATA IN
SLAVE
DATA OUT
SS0 - SS1
High Z
1 2 3 4 N
TSERCDC
TSERDOD
(N-5)SCLK
TSERCEC
Figure 6.4 BSIO Write Operation Timing Diagram