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12: Peripheral Control Logic
114 GP4020 GPS Baseband Processor Design Manual
PLLDT1
UART_CLK
BuILD_CLK
RF_PLL_LOCK
RTC_CLK
NSRESET
POWER_GOOD
EN_POW_RST
F_SLEEP
SFT_RESET
UART_CLK
NRESET
(TO FIREFLY, CORR)
NPOR_RESET
(TO 1PPS, RTC, SCG)
POW_CNTL
REGISTER
UIM ADDRESS & DATA BUSUIM BUS
IO_REV
REGISTER
IP_READ
REGISTER
PER_STAT
[13:0]
REGISTER
NSRST_RESET
WAT_RESET
POW_RESET
PLL_RESET
SFT_RESET
CLR_RST
EN_POW_RST
EN_PLL_RST
PLL_IN_SEL[1:0]
PLL_BYP
B_CLK_SEL[1:0]
F_SLEEP
PLL_SLEEP
RF_SLEEP
WAK_UART
WAK_COR
WAK_DISC
WATCH_EN
POWG_EN
DISCIO_CFG[2:0]
MFNIO_CFG[2:0]
DISCOP_MUX
BSIO_MUX[1:0]
EXT_NCS0
IO_REV[
15:10]
CHIP_REV
[5:0]
TESTMODE
SIGN0
MAG0
TIMEMARK
TIC
MULTI_FNIO_READ
POWER_GOOD
DISCIO_READ
DISCOP
PER_INT
RF_PLL_LOCK
RTC_CMP_INT
POW_GD_INT
TIC_INT
CLR_INT
RCMP_INT_EN
POW_INT_EN
EN_PLL_RST
PLL_IN_SEL[1:0]
PLL_SLEEP
PLL_ENABLE
RESET
LOGIC
MULTIPLEX
LOGIC
UART_CLK
MULTI_FNIO
MULTI_FNIO_READ
GPIO[0:7]
CLK100KHz
GPIO[0:7]
BSIO
TIC
RF_PD
WATCH_TM
WATCH_EN
DISCIO_CFG[2:0]
MFNIO_CFG[2:0]
DISCOP_MUX
BSIO_MUX[1:0]
UART_CLK
BSIO
DISCIP1
DISCIO
DISCIO_READ
WATCH_EN
INTERRUPT
AND WAKE-UP
LOGIC
WATCH_INT
MEAS_INT
ACCUM_INT
UART_INT
RTC_CMP_INT
POWER_GOOD
TIC_INT
DISCIP1
NRESET
WAK_COR
WAK_UART
RCMP_INT_EN
POW_INT_EN
WAK_DISC
PER_INT
NSLP_RESET
RF_SLEEP
PLL_PD
PLL_IN_SEL [1:0]
PLL_BYP
B_CLK_SEL [1:0]
PLL_ENABLE
RF_PD
RF_SLEEP
PLL_PD
PLL_SLEEP
NSRST_RESET
WAT_RESET
POW_RESET
PLL_RESET
CLR_RST
RTC_CMP_INT
POW_GD_INT
TIC_INT
POWER_GOOD
RF_PD
PRX_EN
PLL_PD
CLR_SLEEP
NSLP_RESET
GPIO[0:7]
GPIO[0:7]
DISCOP
TEST
TESTMODE
UIM_TEST
UIM_TEST
SIGN1
MAG1
INT_NCS0 INT_NCS0
EXT_NCS0
INT_NCS0
CLR_RESET
CLR_INT
CLR_INTERRUPT
CLR_RST
"POWER
CONTROL"
LINES TO SCG
POWER_GOOD
POWG_EN
RF_PDOWN
PLL_PDOWN
PRX_PDOWN
PRX_EN
Figure 12.1 Peripheral Control Logic Top-level Block Diagram
• NSRESET (Pin 75 (100-pin package)). This indicates that a RESET has been requested from an external
source, perhaps a Reset Button. A system reset will occur as shown in Figure 12.6 on page 117, if this pin is
taken Low (i.e. '0'). This is the only reset source by which ALL GP4020 registers, which can be reset, are
completely reset (except for the Data Retention Register in TIC_RET within the 1PPS Timemark Generator, and
the Real Time Clock Counters). An active Low pulse of greater than 10ns is required on this pin in order to
guarantee that a reset occurs. The NSRESET pin is the only hardware-reset source that can reset the
PER_STAT [4:0] register bits, used to indicate sources of reset.