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12: Peripheral Control Logic
GP4020 GPS Baseband Processor Design Manual 117
NSRESET
NPOR_RESET
NRESET
RTC_CLK
UART_CLK
3 CYCLES - 150ns
20MHzAny Freq
RTC_CLK period = 30517ns. Rising edge only shown.
Figure 12.6 NSRESET Hardware Reset Generation
WATCH_TM
NPOR_RESET
NRESET
RTC_CLK
UART_CLK
3 CYCLES - 150ns
20MHzAny Freq
RTC_CLK period = 30517ns. Rising edge only shown.
Figure 12.7 Watchdog Hardware Reset Generation
SFT_RESET
NRESET
UART_CLK
3 CYCLES
Any Freq
1 CYCLE
Figure 12.8 SFT_RESET Hardware Reset Generation
As shown in the Reset Logic circuit in Figure 12.2 on page 115, there are two internal reset lines produced in the
GP4020 from the Reset inputs:
1) NPOR_RESET. Used to reset all registers in the Peripheral Control Logic, System Clock Generator and 1PPS
Timemark Generator, and some registers in the Real Time Clock (see below for exceptions). It is derived from