Arm Enterprises GP4020 GPS Receiver User Manual


 
7: 12-Channel Correlator
70 GP4020 GPS Baseband Processor Design Manual
7.6.5 ACCUM_STATUS_C Register - Read Address offset 0x200
ACCUM_STATUS_C is a register containing the state of twelve status bits sampled and latched on the active edge
of every ACCUM_INT (as for ACCUM_STATUS_A). They can also be sampled and latched on request, by
performing a write operation to STATUS.
Bit
No.
Mnemonic Description Reset
Value
R/W
15
Not used
'0' when read 0 R
14
Not used
'0' when read 0 R
13
Not used
'0' when read 0 R
12
Not used
'0' when read 0 R
11 CH11_EARLY_LATEB Status bit which indicates the code type for the accumulated Data on the
Tracking arm of channel 11, when that channel is in Dithering mode.
'1' = EARLY code
'0' = LATE code.
Each individual bit is determined on the DUMP that sets
CHx_NEW_ACCUM_DATA to High for that channel.
0R
10 CH10_EARLY_LATEB (as bit 11 but for channel 10) 0 R
9 CH9_EARLY_LATEB (as bit 11 but for channel 9) 0 R
8 CH8_EARLY_LATEB (as bit 11 but for channel 8) 0 R
7 CH7_EARLY_LATEB (as bit 11 but for channel 7) 0 R
6 CH6_EARLY_LATEB (as bit 11 but for channel 6) 0 R
5 CH5_EARLY_LATEB (as bit 11 but for channel 5) 0 R
4 CH4_EARLY_LATEB (as bit 11 but for channel 4) 0 R
3 CH3_EARLY_LATEB (as bit 11 but for channel 3) 0 R
2 CH2_EARLY_LATEB (as bit 11 but for channel 2) 0 R
1 CH1_EARLY_LATEB (as bit 11 but for channel 1) 0 R
0 CH0_EARLY_LATEB (as bit 11 but for channel 0) 0 R
Table 7.8 CORR ACCUM_STATUS_C Register
Note that the channel specific bits of this register will not show their new value until after an active edge of
ACCUM_INT or a write to the STATUS register. Disabling a channel will however, clear the bit immediately.
7.6.6 CHx_ACCUM_RESET Register - Offset <CHx_Accumulate> + 0x04
Accumulator Status Register reset. A write of any value to this register will reset all of the status bits in
ACCUM_STATUS_A, ACCUM_STATUS_B, and ACCUM_STATUS_C associated with a given channel or all
channels. When these locations are written to, the data is irrelevant.
Bit
No.
Mnemonic Description
Reset
Value
R/W
15:0
Not used
Reset Accumulator Status Registers 0x0000 W
Table 7.9 CORR CHx_ACCUM_RESET Register