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8: DMA Controller
98 GP4020 GPS Baseband Processor Design Manual
1.3) DMAC Channel 2 can only receive DMAC hardware triggers from UART 2, and no other source.
Consequently, the trigger options listed in Table 8.1 do not exist for UART 2 DMAC Fly-by or dual-
addressed transfers.
2) Put DMAC into “Program Mode” to allow DMAC commands to be programmed into DMAC before execution.
This is done by clearing to ”0” the Channel Status bit (bit 0) of the Channel and Control Status Register (CSR)
for the relevant DMAC Channel (UART1 uses Channel 1, UART 2 uses Channel 2).
This allows the DMAC to be programmed with commands, and DMAC operations are suspended until bit 0 is
set to “1”.
Both DMAC channels need to be programmed up at this stage. In this example, we shall use the idea that
DMAC Channel 1 is used to read from memory, and Channel 2 is used to write to memory:
2.1) For both the Channel 1 and Channel 2 Control and Status Register (CSR):
2.1.1) Clear to ”0” the DMAC Hardware Request Status bit (bit 1), to disable Hardware requests (dreq and
dack) from either UART 1 or UART 2 to control the DMAC function.
2.1.2) Clear to “0” the DMAC Software Request bit (bit 2), to disable the Software DMA transfer triggering.
Note that when a software trigger is required after the DMAC is programmed, a write of a "1" to this
register bit will initiate a DMA transfer.
2.1.3) Clear to “0” the DMAC Hardware Acknowledge Status bit (bit 5), to disable the Dack signals from
UARTs 1 and 2.
2.1.4) Clear to “0” the Address Mode bit (bit 6), to allow the dual-addressed location in memory to be
dynamically modified between successive DMA transfers. The Address Direction bit (bit 7) should be
set depending on whether the address location should dynamically increment (bit 7 set to “1”) or
decrement (bit 7 cleared to “0”).
2.1.5) In the DMAC Channel 1 Control and Status Register (CSR), clear to “0” the Transfer Direction bit (bit
8), to signify data is being read from memory. In DMAC Channel 2 Control and Status Register
(CSR), set to “1” the Transfer Direction bit (bit 8), to signify data is being written to memory.
2.1.6) Set to “1” the Transfer Mode bit (bit 9), to signify that Data transfers will be Dual-addressed.
2.1.7) Clear to ”0” the Transfer Type bit (bit 10), to allow Packet Data Transfers to occur.
Packet Data transfers must be used in Dual-addressed transfers if running the ARM7TDMI
simultaneously with a DMA transfer. Packet transfers of one word per packet will allow the ARM to
operate on alternate bus cycles. DMAC Block transfers will stall the ARM7TDMI, which could be fatal
in a GPS system where correlator interrupts MUST be serviced.
2.1.8) Clear to “0” the Request Trigger Type bit (bit 11), to allow enable “Edge-Triggered” Packet Transfers.
Refer to Section 6.2.1.4 in the Firefly MF1 Core Design Manual for details of Edge-triggered Packet
Transfers.
2.1.9) Set the DMAC Operand Size (bits [13:12]), to set the required word-width. Refer to Table 6-3 in the
Firefly MF1 Core Design Manual for details of Operand size settings.
2.1.10) It may be desirable to set-up an Interrupt Service Routine to run in the ARM7TDMI to service a DMAC
Interrupt signal into the Firefly INTC Channel 3 (Refer to Section 10 "INTERRUPT CONTROLLER
(INTC)" on page 107 for information on Interrupt settings). The DMAC interrupt can be generated
under the conditions indicated in section 6.2.3.5 of the Firefly MF1 Core Design Manual (DM5003). If
the Interrupt into the Interrupt Controller (INTC) in Firefly is required, Set to "1" the Interrupt Enable bit
(bit 16) of the DMAC CSR; if NOT required, Clear this bit to "0".
2.1.11) Clear to “0” the Bus Lock bit (bit 17), to prevent the DMAC from being interrupted during a transfer
from a Higher priority BµILD Bus Master (e.g. ARM7TDMI, SSM)