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3: ARM7TDMI
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GP4020 GPS Baseband Processor Design Manual 25
An interrupt impulse to the ARM7TDMI will cause it to exit SLEEP mode. In certain circumstances, this may cause
the ARM7TDMI to enter an UNDEF (Undefined Instruction) trap (to address 0x04). In order to return to normal
program control, a:
MOVS PC,R14_und
instruction should be placed at address 0x04. If the UNDEF trap is to be used for other purposes also, a test
starting at location 0x04 will be necessary, to identify if the trap was as a result of an interrupt whilst in SLEEP
mode.
Note: With the ARM7TDMI processor in SLEEP mode, other Bus Masters (e.g.: DMAC) are still able to utilise the
bus.
3.6.1 Info on the Undefined Instruction Trap
When using the Sleep co-processor, the ARM7TDMI can get an instruction when re-enabled, which it cannot
handle, and it will take an “Undefined Instruction” trap. The trap may be used for software emulation of a
coprocessor in a system, which does not have the coprocessor hardware, or for general purpose instruction set
extension by software emulation.
When ARM7TDMI takes the undefined instruction trap, it performs the following:
1) Saves the address of the Undefined or coprocessor instruction plus four in “R14_und”; saves CPSR in
“SPSR_und”.
2) Forces M[4:0]=’11011’ (Undefined mode) and sets the I bit in the CPSR
3) Forces the PC to fetch the next instruction from address 0x04
To return from this trap after emulating the failed instruction, use:
MOVS PC,R14_und.
This will restore the CPSR and return to the instruction following the undefined instruction.
Further details of the function and programming of the ARM7TDMI microprocessor can be found in Section 2 of the
"Firefly MF1 Core Design Manual" DM5003, available from Zarlink Semiconductor. In addition Rev 3 of the
ARM7TDMI Technical Reference Manual (document reference ARM DDI 0029F), is downloadable (1.7 MB PDF)
from ARM's website http://www.arm.com. The documentation download page can be found at:
http://www.arm.com/arm/documentation?OpenDocument.