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3: ARM7TDMI
TM
Microprocessor
GP4020 GPS Baseband Processor Design Manual 23
• System (sys) A privileged user mode for the operating system
• Undefined (und) Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs will execute in User mode. The non-user modes (“privileged modes”) are
entered in order to service interrupts or exceptions, or to access protected resources.
3.5 Register Sets
In ARM State, 16 general registers and 1 or 2 status registers are visible at any one time. In privileged (non-User)
modes, mode-specific banked registers are switched in. Table 3.3, Table 3.4, Table 3.5, and Table 3.6 below show
which registers are available in each mode: an asterisk indicates the banked registers (*):
System
& User
FIQ Supervisor Abort IRQ Undefined
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8_fiq * R8 R8 R8 R8
R9 R9_fiq * R9 R9 R9 R9
R10 R10_fiq * R10 R10 R10 R10
R11 R11_fiq * R11 R11 R11 R11
R12 R12_fiq * R12 R12 R12 R12
R13 R13_fiq * R13_svc * R13_abt * R13_irq * R13_und *
R14 R14_fiq * R14_svc * R14_abt * R14_irq * R14_und *
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
Table 3.3 ARM State General Registers and Program Counter
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq
*
SPSR_svc
*
SPSR_abt
*
SPSR_irq * SPSR_und *
Table 3.4 ARM State Program Status Registers
* Indicates register is banked.
The Thumb State register set is a subset of the ARM State set. The programmer has direct access to eight general
registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the
CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each
privileged mode.