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6: BSIO Interface
36 GP4020 GPS Baseband Processor Design Manual
READ
BUFFER
WRITE
BUFFER
FREQUENCY
DIVIDER
SLAVE SELECT
LOGIC
INTERRUPT
CONTROL
SEQUENCER
status
status
BSIOCLK
BSIODATA
BSIOSS[0]
INT
EXTERNAL INTERFACE
B_CLK
Status Register
Config & Transfer
Registers
Status
Slave Select
Read Buffer Control
Write Buffer Control
SCLK EN
SCLKX2
Transfer
Register
Config
Register
BuILD
Bus
SCLKX2
CONFSCLK
SCLK_INT
CONFSDIO
Tri_State_En
SDI
SS0_OP
SCLK_TRI_STATE
SCLK_OP
SDO_TRI_STATE
SDO_OP
Tri_State_En
SDO
Config & Transfer
Registers
Config & Transfer
Registers
Config & Transfer
Registers
SCLK_INT
STATUS
Status
Fly-by
BSIO INTERNALS
BSIOSS[1]SS1_OP
Figure 6.2 BµILD Serial Input Output (BSIO) Block Diagram