Filter
Top Products
15: 1PPS Timemark Generator
GP4020 GPS Baseband Processor Design Manual 157
TIC
Event
TIC_
CORR
[2:0]
Phase
Offset
Offset
delay
(ns)
Over
flow
Next TIC
Period (µs)
Cumulated
Overflow
Overflow
delay
(ns)
Total
Delay
(ns)
0 100 0 0 0 99999.9 0 0 0
1 100 4 100 0 99999.9 0 0 100
2 100 1 25 1 100000.075 1 175 200
3 100 5 125 0 99999.9 1 175 300
4 100 2 50 1 100000.075 2 350 400
5 100 6 150 0 99999.9 2 350 500
6 100 3 75 1 100000.075 3 525 600
7 100 0 0 1 100000.075 4 700 700
8 100 4 100 0 99999.9 4 700 800
9 100 1 25 1 100000.075 5 875 900
10 100 5 125 0 99999.9 5 875 1000
Table 15.1 TIC delay calculations for Timemark using TIC period slew, TIC period with zero error
There are five TIC events out of 10, where the TIC period needs to be adjusted, appearing as coarse 'Phase_clock'
corrections inside the correlator core. Timemark output is corrected to the appropriate M_CLK cycle.
15.4.4 Timemark setting example 2; TIC period Slewing with +0.5ppm Receiver Clock Offset
In practice, the TIC period could be upto ±2.5ppm in error due to the Receiver Clock Offset (drift in the receiver
TCXO), which equates to approx. ±250ns in a TIC period of 0.0999999s. When a GPS receiver has acquired four
or more satellite signals, and has achieved a first fix, the receiver should be able to deduce the error in TIC period
due to Receiver Clock offset.
To take the timing example further, assume that the TIC period is in error by -50ns (+0.5ppm. Ppm error is
normally equated to frequency, not time, and so the ppm sign is +, NOT -), giving an actual TIC period of
0.09999985s. This means that the correction needed at each TIC to align to UTC, is +150ns. Therefore, at each
TIC, a value of '110' (six M_CLK cycles) needs to be added to the phase-offset. The process would occur, shown in
Table 15.2 below. TIC Event 0 is assumed phase-aligned to UTC, so the required delay is 0µs.
TIC
Event
TIC_
CORR
[2:0]
Phase
Offset
Offset
delay
(ns)
Over
flow
Next TIC
Period(µs)
Cumulated
Overflow
Overflow
delay (ns)
Total
delay
(ns)
0 110 0 0 0 99999.85 0 0 0
1 110 6 150 0 99999.85 0 0 150
2 110 5 125 1 100000.025 1 175 300
3 110 4 100 1 100000.025 2 350 450
4 110 3 75 1 100000.025 3 525 600
5 110 2 50 1 100000.025 4 700 750
6 110 1 25 1 100000.025 5 875 900
7 110 0 0 1 100000.025 6 1050 1050
8 110 6 150 0 99999.85 6 1050 1200
9 110 5 125 1 100000.025 7 1225 1350
10 110 4 100 1 100000.025 8 1400 1500
Table 15.2 TIC delay calculations for Timemark using TIC period slew, TIC period with +0.5ppm error
There are eight TIC events out of 10, where the TIC period needs to be adjusted, appearing as coarse
'Phase_clock' corrections inside the correlator core. Timemark output is corrected to the appropriate M_CLK cycle.