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1: Introduction
GP4020 GPS Baseband Processor Design Manual 7
Further details of the function and programming System Services Module can be found in Sections 2 and 8 of the
"Firefly MF1 Core Design Manual" DM5003, available from Zarlink Semiconductor.
1.3.17 System Timer/Counters (SYSTIC)
Two dual independent 32-bit timer/counters, with an 8-bit pre-scaler capability for each counter, are provided
(Timers 1A, 1B, 2A and 2B). These are synchronous to the system clock and may be polled, or set-up to generate
interrupts on over-run, with auto-reload.
The TIC functions provided by this module are part of the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020
Base Address 0xE000 E000, and Timer 2 (TIC2) appears at Address 0xE000 F000. TIC enable (TEN) lines are not
available externally on the GP4020, but are tied Low on- chip. The TIC functions can be made available by setting
the External Enable Polarity bit of the TIC Control/Status register to logic “0”.
These timer / counters are NOT required by the GPS function in a GP4020 based GPS receiver. However, full
programming details of the programming of the System Timer/Counter can be found in Section 7 of the "Firefly MF1
Core Design Manual" DM5003, available from Zarlink Semiconductor.
1.3.18 1PPS Timemark Generator (1PPS)
The GP4020 Timemark generator is used in conjunction with software to produce a 1 Pulse-Per-Second (1PPS)
output pulse, which is aligned to Universal Time Co-ordinated (UTC) to a resolution of 25ns. The accuracy of time
transmitted from the Navstar GPS space-segment is very high, and this can be used to provide a mobile timing
reference to a similar accuracy.
Details can be found in section 15 "1PPS TIMEMARK GENERATOR" on page 149.
1.3.19 Up Integration Module (UIM)
This module provides a series of internal connection ports, which mimic the MPC external interface. This allows
customer logic, which has been developed externally and accessed via the MPC interface, to be quickly and
efficiently integrated to produce a complete ASIC.
1.3.20 Universal Asynchronous Receiver Transmitter (UART)
The full duplex asynchronous channel provides an RS232 type interface, which supports a XON/XOFF software
protocol. The Receive and Transmit channels are double buffered. The UART may be either Polled, or use an
interrupt scheme for module bus transfers. An internal Baud rate generator can provide selectable data rates,
derived from on-chip sources for a Rx/Tx pair. Directly triggered DMA transfers with the UART are also possible
without the need for CPU intervention.
Details can be found in section 17 "UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)" on page
169.
1.3.21 Watchdog (WDOG)
The GP4020 Watchdog can be used to detect hardware or software run-time errors, and reset the system. The
processor is required to reset the watchdog periodically; failure to do so will result in a chip-wide reset.
Details can be found in section 18 "WATCHDOG TIMER (WDOG)" on page 176.