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Index - VIII GP4020 GPS Baseband Processor Design Manual
Table 12.8 PCL PER_STAT Register ......................................................................................130
Table 13.1 Real Time Clock Register Map...............................................................................132
Table 13.2 RTC_PRE Register................................................................................................133
Table 13.3 RTC_SEC_B Register............................................................................................133
Table 13.4 RTC COMP_RTCP Register ..................................................................................133
Table 13.5 RTC COMP_RTCS Register ..................................................................................134
Table 14.1 PLL Block Pin Names & Descriptions .....................................................................141
Table 14.2 Valid UART_CLK frequencies that can be produced from M_CLK (from RF Front end)142
Table 14.3 Higher UART_CLK frequencies that can be produced from M_CLK.........................143
Table 14.4 SCG register values for UART_CLK frequencies produced from M_CLK .................144
Table 14.5 PLL configuration options with input freq. from Processor Crystal Oscillator.............145
Table 14.6 System Clock Generator Register Map...................................................................146
Table 14.7 POW_CNTL Register.............................................................................................147
Table 14.8 PLL_CNTL Register...............................................................................................148
Table 15.1 TIC delay calcs for Timemark using TIC period slew, TIC period = zero error...........157
Table 15.2 TIC delay calcs for Timemark using TIC period slew, TIC period = +0.5ppm error....157
Table 15.3 TIC delay calcs for Timemark using TIC period slew, TIC period = +2.5ppm error....158
Table 15.4 TIC delay calcs for Timemark using TIC period slew, TIC period = -2.5ppm error.....159
Table 15.5 TIC delay calcs for Timemark, using Delay Counter - TIC period = zero error...........160
Table 15.6 TIC delay calcs for Timemark, using Delay Counter - TIC period = +0.5ppm error....161
Table 15.7 TIC delay calcs for Timemark, using Delay Counter - TIC period = +2.5ppm error....162
Table 15.8 TIC delay calcs for Timemark, using Delay Counter - TIC period = -2.5ppm error.....163
Table 15.9 1PPS Timemark Generator Register Map...............................................................164
Table 15.10 1PPS Timemark PER_STAT Register ..................................................................164
Table 15.11 1PPS Timemark TIC_RET Register......................................................................165
Table 15.12 1PPS Timemark TIM_DEL_LO Register ...............................................................165
Table 15.13 1PPS Timemark TIM_DEL_HI Register ................................................................166
Table 17.1 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 20MHz..........170
Table 17.2 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 21.25MHz .....171
Table 17.3 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 22.5MHz .......171
Table 17.4 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 23.75MHz .....171
Table 17.5 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 25MHz..........172
Table 17.6 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 26.25MHz .....172
Table 17.7 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 27.5MHz .......172
Table 17.8 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 28.75MHz .....173
Table 17.9 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 30MHz..........173
Table 17.10 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 32.5MHz .....173
Table 17.11 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 35MHz ........174