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3: ARM7TDMI
TM
Microprocessor
GP4020 GPS Baseband Processor Design Manual 19
3 ARM7TDMI MICROPROCESSOR
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general-purpose 32-bit
microprocessors, which offer high performance for very low power consumption and price. The ARM architecture is
based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode
mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers. This simplicity
results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective
core.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically,
while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from
memory.
The ARM memory interface has been designed to allow the performance potential to be realised without incurring
high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be
implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access
modes offered by industry standard dynamic Ram.
The ARM7TDMI microprocessor is surrounded by a scan chain. This allows it to be isolated from the embedded
system for debug purposes. Register or memory values may be examined, and breakpoints and watchpoints may
be set via the JTAG interface. As ARM instructions are conditionally executed, the microprocessor pipeline follows
breakpoints to determine whether a trigger condition exists.
3.1 ARM7TDMI Instruction Set Architecture
The ARM7TDMI microprocessor employs a unique architectural strategy known as Thumb, which makes it ideally
suited to high-volume applications with memory restrictions or applications where high code density is essential.
The ARM 32-bit instruction set offers flexibility in instruction format and operand manipulation while producing
maximum performance from 32-bit memory systems.
3.2 The Thumb Concept
The essential idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI
microprocessor has two instruction sets. The Thumb set’s 16-bit instruction length allows it to approach twice the
density of standard ARM code while retaining most of the ARM7TDMI's performance advantage over a traditional
16-bit microprocessor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit
register set as ARM code.
Thumb code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent
ARM microprocessor connected to a 16-bit memory system.
3.3 Thumb’s Advantages
Thumb instructions operate with the standard ARM register configuration, allowing excellent interoperability
between ARM and Thumb states. Each 16-bit Thumb instruction has a corresponding 32-bit ARM instruction with
the same effect on the microprocessor model.
The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit
integers with single instructions, and to address a large address space efficiently. When processing 32-bit data, a
16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction.
However, not all the code in a program will process 32-bit data (for example, code that performs character string
handling), and some instructions, like Branches, do not process any data at all.