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14: System Clock Generator
GP4020 GPS Baseband Processor Design Manual 147
Bit
No.
Mnemonic Description Reset
Value
R/W
7:6 B_CLK_SEL[1:0] UART_CLK divider block selector.
Allows selection of different output division ratios for the UART_CLK signal,
to allow small resolution changes in UART_CLK frequency, if required. The
divider ratio is set to divide by 1, in the reset condition.
‘00’ = divide by 1 (i.e. through connection)
‘01’ = divide by 2
‘10’ = divide by 4
‘11’ = divide by 8
00 R/W
5 PLL_BYP PLL Bypass connection. Allows input signal to PLL to appear at input to
UART_CLK divider block, effectively removing PLL from signal path. The
PLL is bypassed in the reset condition.
'1' = Enable PLL bypass, remove PLL from the signal path.
'0' = Disable PLL bypass, connect PLL.
1R/W
4:3 PLL_IN_SEL[1:0] PLL Input (& PLL Bypass) signal selector. Allows either divided down
versions of the M_CLK signal (20.0MHz or 10.0MHz) or a signal from the
Processor Crystal Oscillator (10.0MHz to 16.0MHz) to be applied to the PLL
CLKINB input as a PLL reference signal. M_CLK / 2 is applied to the PLL
CLKINB input in the reset condition.
'0x' = connect the output from the Processor Crystal Oscillator to PLL
CLKINB input
'10' = connect M_CLK / 2 (=20MHz) to PLL CLKINB input
'11' = connect M_CLK / 4 (=10.0MHz) to PLL CLKINB input
For each change of state, the PLL will be disabled for a wait period of
approx. 183
µs (6 * 32kHz clock cycles; determined by the Real Time Clock
block). This allows the CLKINB to stabilise.
10 R/W
2 PLL_PD PLL Power Down. PLL is Disabled in the reset Condition
'1' = disable the PLL immediately.
'0' = Enable the PLL after a wait period of approx. 183µs (6 * 32kHz
clock cycles; determined by the Real Time Clock block). This
allows the CLKINB to stabilise.
1R/W
1 PRX_EN Enable Processor Crystal Oscillator block..
'1' = Enable the Processor Crystal Oscillator; start up time in 10ms
typical
'0' = disable the Processor Crystal Oscillator. Only to be done if
UART_CLK is derived directly from M_CLK.
1R/W
0RF_PD
Power Down RF Front-end and 40MHz Low Level Differential
Block. Blocks are powered Up in the Reset Condition.
'1' = disable the Differential Block and apply an active High power-
down signal to the RF Front-end (via DISCIO (pin 55 (100-pin
package)), if so configured (ref. IO_REV register). Only
possible if UART_CLK is derived from the Processor Crystal
Oscillator, as M_CLK will be disabled with the RF Front end.
'0' = re-enable the Differential Block and apply an active Low
power-on signal to the RF Front-end (via DISCIO (pin 55
(100-pin package)), if so configured (ref. IO_REV register).
0R/W
Table 14.7 POW_CNTL Register
Note: Wake up event: event which reverses the Sleep activation mode. These are explained in Section 12.5
"Interrupt and Wake-up logic" on page 121.