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20: Input / Output pin Characteristics
GP4020 GPS Baseband Processor Design Manual 187
Pin
No.
Pin Name Pin
Type
IP / OP Cell
Type
5V
Tol.?
Hold
Cell?
Pull-up/ -
down
Tri-
state
Notes
77 U2RXD IP SCJIP1NR Yes No None -
78 U1TXD OP CLAOP03L1 - - - No
79 U1RXD IP SCJIP1NR Yes No None -
80 PLLGND PWR CLPLLVM
81 PLLVDD PWR CLPLLVP
82 GND PWR CLALLGND
83 PLLAT1 OP CLHANPOP
84 NICE IP CLAIP1NR No No None -
85 VDD PWR CLALLVDD
86
TCK / bdiag[0] / XReq
IP/OP CLAIO1NR01N No No None Yes
87
TDI / bdiag[1] / XWrite
IP/OP CLAIO1NR01N No No None Yes
88
TDO / bdiag[2] /XBurst
IP/OP CLAIO1NR01N No No None Yes
89
TMS / bdiag[3] / XCon
IP/OP CLAIO1NR01N No No None Yes
90 NTRST IP CLAIP1NR No No None -
91 GPIO[7] / DT1 IP/OP SCJIO1NR01N Yes No None Yes
92 GPIO[6] IP/OP SCJIO1NR01N Yes No None Yes
93 GPIO[5]/DISCOP IP/OP SCJIO1NR01N Yes No None Yes
94 GND PWR CLALLGND
95 GPIO[4] /DISCIO IP/OP SCJIO1NR01N Yes No None Yes
96 GPIO[3] / BSIO_SS[1] IP/OP SCJIO1NR01N Yes No None Yes
97 GPIO[2] / BSIO_SS[0] IP/OP SCJIO1NR01N Yes No None Yes
98 VDD PWR CLALLVDD
99 GPIO[1] / BSIO_DATA IP/OP SCJIO1NR01N Yes No None Yes
100 GPIO[0] / BSIO_CLK IP/OP SCJIO1NR01N Yes No None Yes
Table 20.1 GP4020 Pin Types
NOTES:-
1) Pin is set to High Impedance (Tri-state) in RF Power-down mode. RF Power-down achieved when RF_PD bit
or RF_SLEEP bit in PCL POW_CNTL register set to “1”.
2) Pin set to be an Input when GP4020 in Test Mode
3) Pin set to be High Impedance (Tri-state) when GP4020 in Test Mode
20.2 Input Delays
The following tables show the delays for all Logic Inputs on the GP4020. The delays quoted below are shown at
midpoint temperature (+25°C), supply voltage (+3.3V) and silicon process for all input lines in the GP4020.
Key: IP → D ↑ signifies Time from Input going High, to registered Data going High
IP → D ↓ signifies Time from Input going Low, to registered Data going Low
20.2.1 3.3V Inputs: CLAIO1HD01N, CLAIO1HD03N, CLAIO1NR01N, CLAIP1GD, CLAIP1GU,
CLAIP1NR
Switching characteristics at 25°C, 3.3V supply.