Filter
Top Products
TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HPI8 timing (continued)
Valid
t
su(HSL-DSL)
Valid
t
su(HBV-DSL)
t
su(HBV-DSL)
‡
HAS
HBIL
t
h(DSL-HBV)
t
h(DSL-HBV)
‡
t
d(DSH-HYH)
t
w(DSL)
t
d(DSL-HDV1)
t
v(HYH-HDV)
Valid Valid
Valid
t
d(COH-HYH)
Valid
t
w(DSH)
t
d(DSH-HYL)
t
h(DSH-HDV)R
t
h(DSH-HDV)W
Valid
t
su(HDV-DSH)
t
d(DSL-HDV2)
t
en(DSL-HD)
HCS
HDS
HRDY
HD READ
Valid
HD WRITE
CLKOUT
Second Byte First Byte Second Byte
HAD
†
†
HAD
refers to HCNTL0, HCNTL1, and HR/W.
‡
When HAS
is not used (HAS always high)
Figure 35. Using HDS to Control Accesses (HCS Always Low)