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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DMA subbank addressed registers (continued)
Table 12. DMA Subbank Addressed Registers
DMA
NAME ADDRESS
SUB-
ADDRESS
DESCRIPTION
DMSRC0 56h/57h 00h DMA channel 0 source address register
DMDST0 56h/57h 01h DMA channel 0 destination address register
DMCTR0 56h/57h 02h DMA channel 0 element count register
DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register
DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register
DMSRC1 56h/57h 05h DMA channel 1 source address register
DMDST1 56h/57h 06h DMA channel 1 destination address register
DMCTR1 56h/57h 07h DMA channel 1 element count register
DMSFC1 56h/57h 08h DMA channel 1 sync select and frame count register
DMMCR1 56h/57h 09h DMA channel 1 transfer mode control register
DMSRC2 56h/57h 0Ah DMA channel 2 source address register
DMDST2 56h/57h 0Bh DMA channel 2 destination address register
DMCTR2 56h/57h 0Ch DMA channel 2 element count register
DMSFC2 56h/57h 0Dh DMA channel 2 sync select and frame count register
DMMCR2 56h/57h 0Eh DMA channel 2 transfer mode control register
DMSRC3 56h/57h 0Fh DMA channel 3 source address register
DMDST3 56h/57h 10h DMA channel 3 destination address register
DMCTR3 56h/57h 11h DMA channel 3 element count register
DMSFC3 56h/57h 12h DMA channel 3 sync select and frame count register
DMMCR3 56h/57h 13h DMA channel 3 transfer mode control register
DMSRC4 56h/57h 14h DMA channel 4 source address register
DMDST4 56h/57h 15h DMA channel 4 destination address register
DMCTR4 56h/57h 16h DMA channel 4 element count register
DMSFC4 56h/57h 17h DMA channel 4 sync select and frame count register
DMMCR4 56h/57h 18h DMA channel 4 transfer mode control register
DMSRC5 56h/57h 19h DMA channel 5 source address register
DMDST5 56h/57h 1Ah DMA channel 5 destination address register
DMCTR5 56h/57h 1Bh DMA channel 5 element count register
DMSFC5 56h/57h 1Ch DMA channel 5 sync select and frame count register
DMMCR5 56h/57h 1Dh DMA channel 5 transfer mode control register
DMSRCP 56h/57h 1Eh DMA source program page address (common channel)
DMDSTP 56h/57h 1Fh DMA destination program page address (common channel)
DMIDX0 56h/57h 20h DMA element index address register 0
DMIDX1 56h/57h 21h DMA element index address register 1
DMFRI0 56h/57h 22h DMA frame index register 0
DMFRI1 56h/57h 23h DMA frame index register 1
DMGSA 56h/57h 24h DMA global source address reload register
DMGDA 56h/57h 25h DMA global destination address reload register
DMGCR 56h/57h 26h DMA global count reload register
DMGFR 56h/57h 27h DMA global frame count reload register