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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map
Page 0 Program
Hex
Data
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
MP/MC
= 0
(Microcomputer Mode)
MP/MC= 1
(Microprocessor Mode)
0000
007F
0080
FFFF
Reserved
(OVLY = 1)
External
(OVLY = 0)
Interrupts
(External)
FF80
Memory
Mapped
Registers
On-Chip DARAM
(16K x 16-bit)
ROM (DROM=1)
or External
(DROM=0)
0080
FFFF
Hex
0000
FF7F
FF00
FEFF
EFFF
F000
FFFF
3FFF
4000
0060
007F
0000
Hex
Page 0 Program
External
External
Scratch-Pad
RAM
Reserved
(DROM=1)
or External
(DROM=0)
005F
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
3FFF
4000
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
FF00
FEFF
EFFF
F000
External
On-Chip ROM
(4K x 16-bit)
Interrupts
(On-Chip)
3FFF
4000
Reserved
FF7F
FF80
Figure 1. Memory Map
relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS
) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.