Filter
Top Products
TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ready timing for externally generated wait states (continued)
MSC
MSTRB
READY
D[15:0]
A[19:0]
CLKOUT
t
v(MSCH)
t
h(RDY)
Wait State Generated
by READY
Wait States
Generated Internally
t
h(RDY)MSTRB
t
v(RDY)MSTRB
t
v(MSCL)
t
su(RDY)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 18. Memory Write With Externally Generated Wait States