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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
PS, DS
R/W
MSTRB
D[15:0]
A[19:0]
CLKOUT
t
d(CLKH-RWH)
t
h(A)W
t
d(CLKL-MSH)
t
su(D)MSH
t
d(CLKL-D)W
t
w(SL)MS
t
su(A)W
t
d(CLKL-MSL)
t
h(D)MSH
t
d(CLKL-A)
t
d(CLKH-RWL)
t
d(RWL-MSTRBL)
t
d(CLKH-A)
t
en(D-RWL)
t
dis(RWH-D)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 14. Memory Write (MSTRB = 0)