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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME ADDRESS DESCRIPTION TYPE
DRR20 20h McBSP0 data receive register 2 McBSP #0
DRR10 21h McBSP0 data receive register 1 McBSP #0
DXR20 22h McBSP0 data transmit register 2 McBSP #0
DXR10 23h McBSP0 data transmit register 1 McBSP #0
TIM 24h Timer0 register Timer0
PRD 25h Timer0 period counter Timer0
TCR 26h Timer0 control register Timer0
– 27h Reserved
SWWSR 28h Software wait-state register External Bus
BSCR 29h Bank-switching control register External Bus
– 2Ah Reserved
SWCR 2Bh Software wait-state control register External Bus
HPIC 2Ch HPI control register HPI
– 2Dh–2Fh Reserved
TIM1 30h Timer1 register Timer1
PRD1 31h Timer1 period counter Timer1
TCR1 32h Timer1 control register Timer1
– 33h–37h Reserved
SPSA0 38h McBSP0 subbank address register
†
McBSP #0
SPSD0 39h McBSP0 subbank data register
†
McBSP #0
– 3Ah–3Bh Reserved
GPIOCR 3Ch General-purpose I/O pins control register GPIO
GPIOSR 3Dh General-purpose I/O pins status register GPIO
– 3Eh–3Fh Reserved
DRR21 40h McBSP1 data receive register 2 McBSP #1
DRR11 41h McBSP1 data receive register 1 McBSP #1
DXR21 42h McBSP1 data transmit register 2 McBSP #1
DXR11 43h McBSP1 data transmit register 1 McBSP #1
– 44h–47h Reserved
SPSA1 48h McBSP1 subbank address register
†
McBSP #1
SPSD1 49h McBSP1 subbank data register
†
McBSP #1
– 4Ah–53h Reserved
DMPREC 54h DMA channel priority and enable control register DMA
DMSA 55h DMA subbank address register
‡
DMA
DMSDI 56h DMA subbank data register with autoincrement
‡
DMA
DMSDN 57h DMA subbank data register
‡
DMA
CLKMD 58h Clock mode register PLL
– 59h–5Fh Reserved
†
See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.
‡
See Table 12 for a detailed description of the DMA subbank addressed registers.