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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ready timing for externally generated wait states (continued)
t
su(RDY)
MSC
IOSTRB
READY
A[19:0]
CLKOUT
t
v(MSCH)
t
h(RDY)
Wait State Generated
by READY
Wait
States
Generated
Internally
t
v(RDY)IOSTRB
t
v(MSCL)
t
h(RDY)IOSTRB
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 19. I/O Read With Externally Generated Wait States