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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
(n–2)Bit (n–1)
(n–3)(n–2)Bit (n–1)
(n–4)(n–3)(n–2)Bit (n–1)
t
h(BCKRL–BDRV)
t
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
t
su(BDRV–BCKRL)
t
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
t
h(BCKRL–BFRH)
tsu(BFRH–BCKRL)
t
d(BCKRH–BFRV)
t
d(BCKRH–BFRV)
t
r(BCKRX)
t
r(BCKRX)
t
w(BCKRXL)
t
c(BCKRX)
t
w(BCKRXH)
(RDATDLY=10b)
BDR
(RDATDLY=01b)
BDR
(RDATDLY=00b)
BDR
BFSR (ext)
BFSR (int)
BCLKR
Figure 28. McBSP Receive Timings
t
d(BCKXH–BDXV)
t
d(BCKXH–BDXV)
t
dis(BCKXH–BDXHZ)
t
d(BCKXH–BDXV)
t
d(BDFXH–BDXV)
(XDATDLY=10b)
BDX
(XDATDLY=01b)
BDX
(XDATDLY=00b)
BDX
(n–2)Bit (n–1)Bit 0
(n–4)Bit (n–1) (n–3)(n–2)
Bit 0
(n–3)(n–2)Bit (n–1)
Bit 0
t
h(BCKXL–BFXH)
t
f(BCKRX)
t
r(BCKRX)
t
w(BCKRXL)
t
c(BCKRX)
t
w(BCKRXH)
BFSX (ext)
BFSX (int)
BCLKX
t
d(BCKXH–BFXV)
t
d(BCKXH–BFXV)
t
su(BFXH–BCKXL)
Figure 29. McBSP Transmit Timings