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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
timing requirements for a
parallel I/O port read (IOSTRB = 0)
[H = 0.5 t
c(CO)
]
†
(see Figure 15)
MIN MAX UNIT
t
a(A)IO
Access time, read data access from address valid 3H–7 ns
t
a(ISTRBL)IO
Access time, read data access from IOSTRB low 2H–7 ns
t
su(D)IOR
Setup time, read data before CLKOUT high 6 ns
t
h(D)IOR
Hold time, read data after CLKOUT high 0 ns
t
h(ISTRBH-D)R
Hold time, read data after IOSTRB high 0 ns
†
Address and IS timings are included in timings referenced as address.
switching characteristics over recommended operating conditions for a
parallel I/O port read
(IOSTRB
= 0)
†
(see Figure 15)
PARAMETER MIN MAX UNIT
t
d(CLKL-A)
Delay time, CLKOUT low to address valid –2 3 ns
t
d(CLKH-ISTRBL)
Delay time, CLKOUT high to IOSTRB low –2 3 ns
t
d(CLKH-ISTRBH)
Delay time, CLKOUT high to IOSTRB high –2 3 ns
t
h(A)IOR
Hold time, address after CLKOUT low 0 3 ns
†
Address and IS timings are included in timings referenced as address.
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
t
h(A)IOR
t
d(CLKH-ISTRBH)
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
t
d(CLKH-ISTRBL)
t
d(CLKL-A)
t
a(ISTRBL)IO
t
h(ISTRBH-D)R
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 15. Parallel I/O Port Read (IOSTRB = 0)