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TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA
, [H = 0.5 t
c(CO)
] (see Figure 21)
MIN MAX UNIT
t
w(HOLD)
Pulse duration, HOLD low 4H+7 ns
t
su(HOLD)
Setup time, HOLD low/high before CLKOUT low 7 ns
switching characteristics over recommended operating conditions for memory control signals
and HOLDA
, [H = 0.5 t
c(CO)
] (see Figure 21)
PARAMETER MIN MAX UNIT
t
dis(CLKL-A)
Disable time, address, PS, DS, IS high impedance from CLKOUT low 5 ns
t
dis(CLKL-RW)
Disable time, R/W high impedance from CLKOUT low 5 ns
t
dis(CLKL-S)
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 5 ns
t
en(CLKL-A)
Enable time, address, PS, DS, IS from CLKOUT low 2H+5 ns
t
en(CLKL-RW)
Enable time, R/W enabled from CLKOUT low 2H+5 ns
t
en(CLKL-S)
Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2 2H+5 ns
t
Valid time, HOLDA low after CLKOUT low
–1 2 ns
t
v(HOLDA)
Valid time, HOLDA high after CLKOUT low
–1 2 ns
t
w(HOLDA)
Pulse duration, HOLDA low duration 2H–1 ns
IOSTRB
MSTRB
R/W
D[15:0]
PS
, DS, IS
A[19:0]
HOLDA
HOLD
CLKOUT
t
en(CLKL-S)
t
en(CLKL-S)
t
en(CLKL-RW)
t
dis(CLKL-S)
t
dis(CLKL-S)
t
dis(CLKL-RW)
t
dis(CLKL-A)
t
v(HOLDA)
t
v(HOLDA)
t
w(HOLDA)
t
w(HOLD)
t
su(HOLD)
t
su(HOLD)
t
en(CLKL-A)
Figure 21. HOLD and HOLDA Timings (HM = 1)