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48 Using the Matrix Modules Chapter 3
• The FIFO Interface PAL reads the Data Bus and Address Bus
FIFO until the EMPTY* flag signals the FIFO Interface PAL the
FIFO memory is empty.
• When the FIFO is empty, the FIFO Interface PAL signals the VME
Timing PAL which asserts IRQ*. This interrupts the command
module CPU after the last relay has been activated.
• Because the matrix module asserts IRQ* after the last relay is
activated, the CPU is not continually interrupted. Thus, system
throughput is enhanced.
Figure 3-3. Matrix Modules Block Diagram
Decoder
Add
Driver
& One Shot
FIFO
Address
Bus
Detector
Add
Card
Add
Bus
Sysreset
Reset &
& Control
Logic
Card
Card Reset*
PAL
FIFO
Interface
Empty *
PAL
VME
Timing
DTACK
IRQ*
Buffer
Bus
Data
Data
Bus
Bus
FIFO
Data
FIFO-Write
FIFO-Read
Driver
Data
Bus
Device
Register
Register
Status &
ID
Control
Power
Latching
Relay
Ground
Power
Bus