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Chapter 5 Controls, Indicators and Connector Pin Assignments
ATCA-C110/1G Installation and Use Manual
55
REVIEW COPY
AMC4_SATA0_TX+ S4+ 7 43 S22+ AMC4_PCIEXP_LANE1_TX+
AMC4_SATA0_TX- S4- 8
44 S22- AMC4_PCIEXP_LANE1_TX-
AMC4_SATA1_TX+ S5+ 9
45 S23+ AMC4_PCIEXP_LANE2_TX+
AMC4_SATA1_TX- S5- 10
46 S23- AMC4_PCIEXP_LANE2_TX-
AMC3_PCIEXP_LANE0_TX+ S6+ 11
47 S24+ AMC4_PCIEXP_LANE3_TX+
AMC3_PCIEXP_LANE0_TX- S6- 12
48 S24- AMC4_PCIEXP_LANE3_TX-
AMC3_PCIEXP_LANE1_TX+ S7+ 13
49 S25+ AMC3_GBE0_RX+
AMC3_PCIEXP_LANE1_TX- S7- 14
50 S25- AMC3_GBE0_RX-
AMC3_PCIEXP_LANE2_TX+ S8+ 15
51 S26+ AMC3_GBE1_RX+
AMC3_PCIEXP_LANE2_TX- S8- 16
52 S26- AMC3_GBE1_RX-
AMC3_PCIEXP_LANE3_TX+ S9+ 17
53 S27+ AMC3_SATA0_RX+
AMC3_PCIEXP_LANE3_TX- S9- 18
54 S27- AMC3_SATA0_RX-
AMC4_GBE0_RX+ S10+ 19
55 S28+ AMC3_SATA1_RX+
AMC4_GBE0_RX- S10- 20
56 S28- AMC3_SATA1_RX-
AMC4_GBE1_RX+ S11+ 21
57 S29+ AMC4_PCIEXP_LANE0_RX+
AMC4_GBE1_RX- S11- 22
58 S29- AMC4_PCIEXP_LANE0_RX-
AMC4_SATA0_RX+ S12+ 23
59 S30+ AMC4_PCIEXP_LANE1_RX+
AMC4_SATA0_RX- S12- 24
60 S30- AMC4_PCIEXP_LANE1_RX-
AMC4_SATA1_RX+ S13+ 25
61 S31+ AMC4_PCIEXP_LANE2_RX+
AMC4_SATA1_RX- S13- 26
62 S31- AMC4_PCIEXP_LANE2_RX-
AMC3_PCIEXP_LANE0_RX+ S14+ 27
63 S32+ AMC4_PCIEXP_LANE3_RX+
AMC3_PCIEXP_LANE0_RX- S14- 28
64 S32- AMC4_PCIEXP_LANE3_RX-
AMC3_PCIEXP_LANE1_RX+ S15+ 29
65 S33+ MPC_I2C_SCL
AMC3_PCIEXP_LANE1_RX- S15- 30
66 S33- MPC_I2C_SDA
AMC3_PCIEXP_LANE2_RX+ S16+ 31
67 S34+ PVT_I2C_SCL
AMC3_PCIEXP_LANE2_RX- S16- 32
68 S34- PVT_I2C_SDA
AMC3_PCIEXP_LANE3_RX+ S17+ 33
69 S35+ BCM_GBE_MDIO
AMC3_PCIEXP_LANE3_RX- S17- 34
70 S35- BCM_GBE_MDC
AMC3_GBE0_TX+ S18+ 35
71 S36+ AMC3_GBE1_TX+
AMC3_GBE0_TX- S18- 36
72 S36- AMC3_GBE1_TX-
Table 5-3. FIM Connector J1 Pinout (continued)
Signal Pin
Name
Pin # Pin # Pin
Name
Signal