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Chapter 4 Functional Description
ATCA-C110/1G Installation and Use Manual
39
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■ Delivering interrupts to the CPU for servicing
All the interrupts generated on the ATCA-C110 are wired to the interrupt controller of the
MPC8540 Processor. Refer to the Interrupt Mapping on page 72 for the Interrupt Architecture.
I
2
C Interface
The I
2
C Interface on the ATCA-C110/1G is a bi-directional serial bus that provides a simple
efficient, out-band signaling method of data exchange between this device and other devices.
It supports multiple-master operation, and a software-programmable clock frequency.
The I
2
C Controller operates in four different modes:
■ Master mode
■ Slave mode
■ Interrupt driven byte-to-byte transfer
■ Boot sequencer mode
DUART Controller
The DUART of the MPC8540 consists of two Universal Asynchronous Receiver Transmitters
(UARTs). Refer to Serial interface on page 49 for details about the serial devices attached to
the DUART controller.
Local Bus Controller (LBC)
The LBC of the MPC8540 supports the GPCM (General Purpose Chipselect Machine)
interface. The GPCM provides interfacing for simpler, lower-performance memories and
memory-mapped devices. A 2 MB Boot Flash, a Recovery Flash and 64/128 MB User Flash
are mounted on the GPCM interface.
Three Speed Ethernet Controllers (TSEC)
The MPC8540 integrates two three-speed Ethernet Controllers (TSEC1 and TSEC2)
supporting 10/100/1000 Mbps MII/GMII interface operation. The TSECs on the ATCA-C110/1G
implement a Gigabit Ethernet protocol, which builds on top of the Ethernet protocol, but
increases speed tenfold over 10/100 Ethernet to 1000 Mbps or one Gbps.
Fast Ethernet Controller
The MPC8540 Processor provides a Fast Ethernet Controller (FEC) apart from the TSECs
used for the Gigabit Ethernet. The FEC is designed to support 10/100 Mbps, supporting both
half and full duplex operations.
DMA Controller
The DMA Controller of the MPC8540 allows DMA transfers between PCI, the local bus
controller (LBC) interface, and the local address space, independent of the e500 core or
external hosts.