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ATCA-C110/1G Installation and Use Manual
Chapter 4 Functional Description
38
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Processor and Processor interfaces
CPU
ATCA-C110/1G has MPC8540 as a Service Processor working with the following features:
■ e500 high performance PowerPC core
■ Core operating frequency upto 833 Mhz
■ 32 KB L1 data and 32 KB L1 instruction cache with line locking support
■ 256 KB on-chip L2 cache with direct mapped capability
■ Memory Management Unit
CPU Interfaces
■ Universal 64-bit and 66 MHz PCI interface
■ Local bus speed of approximately 82 MHz
■ Two triple-speed Ethernet controllers (TSECs) supporting 10/100/1000 Mbps Ethernet
(IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII
interfaces
■ 166 MHz, 64-bit, 2.5V I/O, DDR SDRAM memory controller with full ECC support
■ 133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 bus controller
■ 166 MHz, 32-bit, 3.3V I/O, local bus with memory controller
■ 10/100 Ethernet controller (802.3)
■ Integrated four-channel DMA controller
■ Interrupt controller
■ IEEE 1149.1 JTAG test access port
Listed below are some of the processor interfaces. The following sections define the CPU
interfaces of the MPC8540 Processor, and briefly describe how these blocks interact with one
another and with other blocks on the device.
Integrated Memory Controller
The fully programmable DDR SDRAM controller integrated in the MPC8540 Processor,
supports first-generation JEDEC standard x8 or x16 DDR memories available, including
buffered and unbuffered DIMMs. The Integrated Memory Controller does not provide direct
support for x4 DDR memories.
Programmable Interrupt Controller
The interrupt controller provides interrupt management and is responsible for the following:
■ Receiving hardware-generated interrupts from internal and external sources
■ Prioritizing interrupts